参数资料
型号: AD9785BSVZ
厂商: Analog Devices Inc
文件页数: 24/64页
文件大小: 0K
描述: IC DAC 12BIT 800MSPS 100TQFP
产品培训模块: Data Converter Fundamentals
DAC Architectures
标准包装: 1
系列: TxDAC®
位数: 12
数据接口: 串行
转换器数目: 2
电压电源: 模拟和数字
功率耗散(最大): 450mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 100-TQFP 裸露焊盘
供应商设备封装: 100-TQFP-EP(14x14)
包装: 托盘
输出数目和类型: 2 电流,单极;2 电流,双极
采样率(每秒): 800M
产品目录页面: 785 (CN2011-ZH PDF)
AD9785/AD9787/AD9788
Rev. A | Page 30 of 64
The Auxiliary DAC 1 control register comprises two bytes located at Address 0x06. These bits are routed directly to the periphery of the
digital logic. No digital functionality within the main digital block is required.
Table 16. Auxiliary DAC 1 Control Register
Address
Bit
Name
Description
0x06
[15]
Auxiliary DAC 1 sign
0: Default. If the Auxiliary DAC 1 sign bit is cleared, the Aux DAC 1 sign is positive.
Pin 90 is the active pin.
1: If the Auxiliary DAC 1 sign bit is set, the Aux DAC 1 sign is negative. Pin 89 is the
active pin.
[14]
Auxiliary DAC 1
current direction
0: Default. If the Auxiliary DAC 1 current direction bit is cleared, the Aux DAC 1 sources
current.
1: If the Auxiliary DAC 1 current direction bit is set, the Aux DAC 1 sinks current.
[13]
Auxiliary DAC 1
power-down
0: Default. If the Auxiliary DAC 1 power-down bit is cleared, the Aux DAC 1 is active.
1: If the Auxiliary DAC 1 power-down bit is set, the Aux DAC 1 is inactive and enters a
low power state.
[12:10]
Reserved
Reserved for future use.
[9:0]
Auxiliary DAC 1 data
These bits are the Auxiliary DAC 1 gain adjustment bits.
The Q DAC control register comprises two bytes located at Address 0x07. These bits are routed directly to the periphery of the digital
logic. No digital functionality within the main digital block is required.
Table 17. Q DAC Control Register
Address
Bit
Name
Description
0x07
[15]
Q DAC sleep
0: Default. If the Q DAC sleep bit is cleared, the Q DAC is active.
1: If the Q DAC sleep bit is set, the Q DAC is inactive and enters a low power state.
[14]
Q DAC power-down
0: Default. If the Q DAC power-down bit is cleared, the Q DAC is active.
1: If the Q DAC power-down bit is set, the Q DAC is inactive and enters a low power state.
[13:10]
Reserved
Reserved for future use.
[9:0]
Q DAC gain adjustment
These bits are the Q DAC gain adjustment bits.
The Auxiliary DAC 2 control register comprises two bytes located at Address 0x08. These bits are routed directly to the periphery of the
digital logic. No digital functionality within the main digital block is required.
Table 18. Auxiliary DAC 2 Control Register
Address
Bit
Name
Description
0x08
[15]
Auxiliary DAC 2 sign
0: Default. If the Auxiliary DAC 2 sign bit is cleared, the Aux DAC 2 sign is positive.
Pin 86 is the active pin.
1: If the Auxiliary DAC 2 sign bit is set, the Aux DAC 2 sign is negative. Pin 87 is the
active pin.
[14]
Auxiliary DAC 2
current direction
0: Default. If the Auxiliary DAC 2 current direction bit is cleared, the Aux DAC 2 sources
current.
1: If the Auxiliary DAC 2 current direction bit is set, the Aux DAC 2 sinks current.
[13]
Auxiliary DAC 2
power-down
0: Default. If the Auxiliary DAC 2 power-down bit is cleared, the Aux DAC 2 is active.
1: If the Auxiliary DAC 2 power-down bit is set, the Aux DAC 2 is inactive and enters
a low power state.
[12:10]
Reserved
Reserved for future use.
[9:0]
Auxiliary DAC 2 data
These bits are the Auxiliary DAC 2 gain adjustment bits.
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