参数资料
| 型号： | AD9785BSVZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 39/64页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT 800MSPS 100TQFP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1,000 |
| 系列： | TxDAC® |
| 位数： | 12 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 450mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-TQFP 裸露焊盘 |
| 供应商设备封装： | 100-TQFP-EP（14x14） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 2 电流，单极；2 电流，双极 |
| 采样率（每秒）： | 800M |
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AD9785/AD9787/AD9788
Rev. A | Page 44 of 64
SYNCHRONIZING DEVICES TO A SYSTEM CLOCK
The AD9785/AD9787/AD9788 offer a pulse mode synchron-
ization scheme (see Figure 61) to align the DAC outputs of
multiple devices within a system to the same DAC clock edge.
The pulse mode synchronization scheme is a two-part
operation. First, the internal clocks are synchronized by
providing either a one-time pulse or periodic signal to the
SYNC_I (SYNC_I+/SYNC_I) inputs. The SYNC_I signal is
sampled by the internal DACCLK sample rate clock.
The SYNC_I input frequency has the following two constraints:
N
f
DAC
IN
SYNC
DATACLK
IN
SYNC
16
_
where N is an integer.
When the internal clocks are synchronized, the data sampling
clocks between all devices are phase aligned. The next step
requires a simultaneous strobe signal to the TXENABLE pin of
all devices that is synchronous to the DATACLK signal. This
resets the phase accumulator of the NCOs across all devices,
effectively synchronizing the NCOs. The strobe signal is
sampled by fDATACLK and must meet the same setup and hold
times as the input data. Because the TXENABLE pin is an active
high logic level pin, the strobe signal should be a low logic level
pulse unless the TXENABLE invert bit is set in the SPI.
For this synchronization scheme, all devices are slave devices,
while the system clock generation/distribution chip serves as
the master. The external LVDS signal should be connected to the
SYNC_I inputs of all the slave devices following the constraints.
The DAC clock inputs and the SYNC_I inputs must be matched
in length across all devices.
It is vital that the SYNC_I signal be distributed between the
DACs with low skew. Likewise, the REFCLK signals must be
distributed with low skew. Any skew on these signals between
the DACs must be accounted for in the timing budget. The
SYNC_I signal is sampled at the DACCLK rate, thus the data
valid window of the SYNC_I pulse must be presented to all the
DACs within the same DACCLK period.
Figure 62 shows the timing of the SYNC_I input with respect to
the REFCLK input. Note that although the timing is relative to
the REFCLK signal, SYNC_I is sampled at the DACCLK rate.
This means that the rising edge of the SYNC_I signal must
occur after the hold time of the preceding DACCLK rising edge
and not the preceding REFCLK rising edge. Figure 63 shows a
timing diagram of the TXENABLE input.
DACCLK
REFCLK
SYNC_I
tS_SYNC
tH_SYNC
07
09
8-
1
06
Figure 62. Timing Diagram of SYNC_I with Respect to REFCLK
REFCLK
DATACLK
TXENABLE
tHREFCLK
tSREFCLK
tSDATACLK
tHDATACLK
07
09
8-
10
5
Figure 63. Timing Diagram of TXENABLE vs. DATACLK and REFCLK
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| AD9785-DPG2-EBZ | 功能描述:BOARD EVALUATION FOR AD9785 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:TxDAC® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9785-EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9785 制造商:Analog Devices 功能描述:DUAL 12B, 1GSPS D-A CONVERTER - Bulk 制造商:Analog Devices 功能描述:Digital to Analog Eval. Board |
| AD9786 | 制造商:AD 制造商全称:Analog Devices 功能描述:16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing |
| AD9786BSV | 制造商:Analog Devices 功能描述:DAC 1-CH Interpolation Filter 16-bit 80-Pin TQFP EP 制造商:Analog Devices 功能描述:IC 16BIT DAC SMD 9786 TQFP80 |
| AD9786BSVRL | 制造商:Analog Devices 功能描述:DAC 1-CH Interpolation Filter 16-bit 80-Pin TQFP EP T/R |
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