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| 型号： | AD9832BRUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/28页 |
| 文件大小： | 0K |
| 描述： | IC DDS 10BIT 25MHZ CMOS 16TSSOP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 2,500 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 25MHz |
| 调节字宽（位）： | 32 b |
| 电源电压： | 2.97 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
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AD9832
Data Sheet
Rev. E | Page 20 of 28
AD9832 TO 68HC11/68L11 INTERFACE
Figure 29 shows the serial interface between the AD9832 and
the 68HC11/68L11 microcontroller. The microcontroller is
configured as the master by setting bit MSTR in the SPCR to 1,
which provides a serial clock on SCK while the MOSI output
drives the serial data line SDATA. Because the microcontroller does
not have a dedicated frame sync pin, the FSYNC signal is derived
from a port line (PC7). The setup conditions for correct operation
of the interface are as follows: SCK idles high between write
operations (CPOL = 0), and data is valid on SCK falling edge
(CPHA = 1). When data is transmitted to the AD9832, the FSYNC
line is taken low (PC7). Serial data from the 68HC11/68L11 is
transmitted in 8-bit bytes with only 8 falling clock edges occurring
in the transmit cycle. Data is transmitted MSB first. To load
data into the AD9832, PC7 is held low after the first 8 bits are
transferred and a second serial write operation is performed to
the AD9832. Only after the second 8 bits have been transferred
should FSYNC be taken high again.
AD9832*
FSYNC
SDATA
SCLK
68HC11/68L11*
PC7
MOSI
SCK
*ADDITIONAL PINS OMITTED FOR CLARITY.
09090-
029
Figure 29. 68HC11/68L11 to AD9832 Interface
AD9832 TO 80C51/80L51 INTERFACE
Figure 30 shows the serial interface between the AD9832 and
the 80C51/80L51 microcontroller. The microcontroller operates
in Mode 0 so that TXD of the 80C51/80L51 drives SCLK of the
AD9832, while RXD drives the serial data line SDATA. The FSYNC
signal is again derived from a bit programmable pin on the port
(P3.3 being used in the diagram). When data is transmitted to
the AD9832, P3.3 is taken low. The 80C51/80L51 transmits data
in 8-bit bytes; therefore, only 8 falling SCLK edges occur in each
cycle. To load the remaining 8 bits to the AD9832, P3.3 is held
low after the first 8 bits have been transmitted and a second
write operation is initiated to transmit the second byte of data.
P3.3 is taken high following the completion of the second write
operation. SCLK should idle high between the two write operations.
The 80C51/80L51 outputs the serial data in a format that has
LSB first. The AD9832 accepts MSB first (the 4 MSBs being the
control information, the next 4 bits being the address, while the
8 LSBs contain the data when writing to a destination register).
Therefore, the transmit routine of the 80C51/80L51 must consider
this format and rearrange the bits so that the MSB is output first.
AD9832*
FSYNC
SDATA
SCLK
80C51/80L51*
P3.3
RxD
TxD
*ADDITIONAL PINS OMITTED FOR CLARITY.
09090-
030
Figure 30. 80C51/80L51 to AD9832 Interface
AD9832 TO DSP56002 INTERFACE
Figure 31 shows the interface between the AD9832 and the
DSP56002. The DSP56002 is configured for normal mode
asynchronous operation with a gated internal clock (SYN = 0,
GCK = 1, SCKD = 1). The frame sync pin is generated internally
(SC2 = 1), the transfers are 16-bits wide (WL1 = 1, WL0 = 0),
and the frame sync signal frames the 16 bits (FSL = 0). The
frame sync signal is available on Pin SC2, but it needs to be
inverted before being applied to the AD9832. The interface to the
DSP56000/DSP56001 is similar to that of the DSP56002.
AD9832*
FSYNC
SDATA
SCLK
DSP56002*
SC2
STD
SCK
*ADDITIONAL PINS OMITTED FOR CLARITY.
09090-
031
Figure 31. AD9832 to DSP56002 Interface
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9832BRUZ-REEL7 | 功能描述:IC DDS 10BIT 25MHZ CMOS 16TSSOP RoHS:是 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| AD9833 | 制造商:AD 制造商全称:Analog Devices 功能描述:+2.5 V to +5.5 V, 25 MHz Low Power CMOS Complete DDS |
| AD9833BRM | 功能描述:IC WAVEFORM GEN PROG 10-MSOP RoHS:否 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| AD9833BRM-REEL | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 25MHz 1-DAC 10-Bit Serial 10-Pin MSOP T/R 制造商:Analog Devices 功能描述:PROGRAMMABLE WAVEFORM GENERATOR 10MSOP - Tape and Reel |
| AD9833BRM-REEL7 | 功能描述:IC WAVEFORM GEN PROG 10-MSOP RoHS:否 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
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