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| 型号： | AD9837ACPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/28页 |
| 文件大小： | 0K |
| 描述： | IC WAVEFORM GEN PROG 10LFCSP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 5,000 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 5MHz |
| 调节字宽（位）： | 28 b |
| 电源电压： | 2.3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘，CSP |
| 供应商设备封装： | 10-LFCSP-WD（3x3） |
| 包装： | 带卷 (TR) |
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Data Sheet
AD9837
Rev. A | Page 15 of 28
FREQUENCY AND PHASE REGISTERS
The AD9837 contains two frequency registers and two phase
registers, which are described in Table 8.
Table 8. Frequency and Phase Registers
Register
Size
Description
FREQ0
28 bits
Frequency Register 0.
When the FSEL bit = 0, the FREQ0
register defines the output frequency
as a fraction of the MCLK frequency.
FREQ1
28 bits
Frequency Register 1.
When the FSEL bit = 1, the FREQ1
register defines the output frequency
as a fraction of the MCLK frequency.
PHASE0
12 bits
Phase Offset Register 0.
When the PSEL bit = 0, the contents of
the PHASE0 register are added to the
output of the phase accumulator.
PHASE1
12 bits
Phase Offset Register 1.
When the PSEL bit = 1, the contents of
the PHASE1 register are added to the
output of the phase accumulator.
The analog output from the AD9837 is
fMCLK/228 × FREQREG
where FREQREG is the value loaded into the selected frequency
register.
This signal is phase shifted by
2π/4096 × PHASEREG
where PHASEREG is the value contained in the selected phase
register.
The relationship of the selected output frequency and the refer-
ence clock frequency must be considered to avoid unwanted
output anomalies.
The flowchart in Figure 24 shows the routine for writing to the
frequency and phase registers of the AD9837.
Writing to a Frequency Register
When writing to a frequency register, Bit D15 and Bit D14 of
the control register give the address of the frequency register
(see Table 9).
Table 9. Frequency Register Bits
D15
D14
D13 to D0
0
1
14 FREQ0 register bits
1
0
14 FREQ1 register bits
To change the entire contents of a frequency register, two consec-
utive writes to the same address must be performed because the
frequency registers are 28 bits wide. The first write contains the
14 LSBs, and the second write contains the 14 MSBs. For this
mode of operation, the B28 control bit (Bit D13) must be set
to 1. An example of a 28-bit write is shown in Table 10.
Table 10. Writing 0xFFFC000 to the FREQ0 Register
SDATA Input
Result of Input Word
0010 0000 0000 0000
Control word write
(D15, D14 = 00), B28 (D13) = 1,
HLB (D12) = X
0100 0000 0000 0000
FREQ0 register write
(D15, D14 = 01), 14 LSBs = 0x0000
0111 1111 1111 1111
FREQ0 register write
(D15, D14 = 01), 14 MSBs = 0x3FFF
Note, however, that continuous writes to the same frequency
register may result in intermediate updates during the writes. If
a frequency sweep, or something similar, is required, it is recom-
mended that users alternate between the two frequency registers.
In some applications, the user does not need to alter all 28 bits
of the frequency register. With coarse tuning, only the 14 MSBs
are altered; with fine tuning, only the 14 LSBs are altered. By
setting the B28 control bit (Bit D13) to 0, the 28-bit frequency
register operates as two 14-bit registers, one containing the
14 MSBs and the other containing the 14 LSBs. In this way, the
14 MSBs of the frequency word can be altered independently
of the 14 LSBs, and vice versa. The HLB bit (Bit D12) in the
control register identifies which 14 bits are being altered (see
Table 11. Writing 0x3FFF to the 14 LSBs of the FREQ1 Register
SDATA Input
Result of Input Word
0000 0000 0000 0000
Control word write
(D15, D14 = 00), B28 (D13) = 0,
HLB (D12) = 0, that is, LSBs
1011 1111 1111 1111
FREQ1 register write
(D15, D14 = 10), 14 LSBs = 0x3FFF
Table 12. Writing 0x00FF to the 14 MSBs of the FREQ0 Register
SDATA Input
Result of Input Word
0001 0000 0000 0000
Control word write
(D15, D14 = 00), B28 (D13) = 0,
HLB (D12) = 1, that is, MSBs
0100 0000 1111 1111
FREQ0 register write
(D15, D14 = 01), 14 MSBs = 0x00FF
Writing to a Phase Register
When writing to a phase register, Bit D15 and Bit D14 are set to
11. Bit D13 identifies the phase register that is being loaded.
Table 13. Phase Register Bits
D15
D14
D13
D12
D11 to D0
1
0
X
12 PHASE0 register bits
1
X
12 PHASE1 register bits
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