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参数资料
| 型号： | AD9854/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/52页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9854 |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 设计资源： | AD9854 Eval Brd Schematic AD9854 Eval Brd BOM |
| 标准包装： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 计时，直接数字合成（DDS） |
| 已用 IC / 零件： | AD9854 |
| 已供物品： | 板 |
| 相关产品： | AD9854ASTZ-ND - IC DDS QUADRATURE CMOS 80-LQFP |
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AD9854
Rev. E | Page 19 of 52
THEORY OF OPERATION
The AD9854 quadrature output digital synthesizer is a highly
flexible device that addresses a wide range of applications. The
device consists of an NCO with a 48-bit phase accumulator, a
programmable reference clock multiplier, inverse sinc filters,
digital multipliers, two 12-bit/300 MHz DACs, a high speed
analog comparator, and interface logic. This highly integrated
device can be configured to serve as a synthesized LO, an agile
clock generator, or an FSK/BPSK modulator.
Analog Devices, Inc., provides a technical tutorial about the
operational theory of the functional blocks of the device. The
tutorial includes a technical description of the signal flow
through a DDS device and provides basic applications
information for a variety of digital synthesis implementations.
The document, A Technical Tutorial on Digital Signal Synthesis,
is available from the DDS Technical Library, on the Analog
Devices DDS website at www.analog.com/dds.
MODES OF OPERATION
The AD9854 has five programmable operational modes. To
select a mode, three bits in the control register (parallel Address
1F hex) must be programmed, as described in Table 5.
Table 5. Mode Selection Table
Mode 2
Mode 1
Mode 0
Result
0
Single tone
0
1
FSK
0
1
0
Ramped FSK
0
1
Chirp
1
0
BPSK
In each mode, some functions may be prohibited. Table 6 lists
the functions and their availability for each mode.
Single Tone (Mode 000)
This is the default mode when the MASTER RESET pin is
asserted. It can also be accessed if the user programs this mode
into the control register. The phase accumulator, responsible for
generating an output frequency, is presented with a 48-bit value
from the Frequency Tuning Word 1 registers that have default
values of 0. Default values from the remaining applicable
registers further define the single-tone output signal qualities.
The default values after a master reset configure the device
with an output signal of 0 Hz and zero phase. At power-up and
reset, the output from the I and Q DACs is a dc value equal to
the midscale output current. This is the default mode amplitude
setting of 0. See the On/Off Output Shaped Keying (OSK)
section for more details about the output amplitude control. All
or some of the 28 program registers must be programmed to
produce a user-defined output signal.
Figure 35 shows the transition from the default condition
(0 Hz) to a user-defined output frequency (F1).
Table 6. Functions Available for Modes
Mode
Function
Single Tone
FSK
Ramped FSK
Chirp
BPSK
Phase Adjust 1
●
Phase Adjust 2
●
Single-Pin FSK/BPSK or HOLD
●
Single-Pin Shaped Keying
●
Phase Offset or Modulation
●
Amplitude Control or Modulation
●
Inverse Sinc Filter
●
Frequency Tuning Word 1
●
Frequency Tuning Word 2
●
Automatic Frequency Sweep
●
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