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| 型号： | AD9854/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/52页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9854 |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 设计资源： | AD9854 Eval Brd Schematic AD9854 Eval Brd BOM |
| 标准包装： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 计时，直接数字合成（DDS） |
| 已用 IC / 零件： | AD9854 |
| 已供物品： | 板 |
| 相关产品： | AD9854ASTZ-ND - IC DDS QUADRATURE CMOS 80-LQFP |
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AD9854
Rev. E | Page 13 of 52
Figure 10 to Figure 15 show the trade-off in elevated noise floor, increased phase noise (PN), and discrete spurious energy when the internal
REFCLK multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown. Compare the noise floor of
Figure 11 and Figure 12 with that of Figure 14 and Figure 15. The improvement seen in Figure 11 and Figure 12 is a direct result of
sampling the fundamental at a higher rate. Sampling at a higher rate spreads the quantization noise of the DAC over a wider bandwidth,
which effectively lowers the noise floor.
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
100kHz/
SPAN 1MHz
0
06
36-
0
10
Figure 10. Narrow-Band SFDR, 39.1 MHz, 1 MHz BW,
300 MHz REFCLK with REFCLK Multiplier Bypassed
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5kHz/
SPAN 50kHz
00
636
-011
Figure 11. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
300 MHz REFCLK with REFCLK Multiplier Bypassed
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5kHz/
SPAN 50kHz
006
36
-0
14
Figure 12. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
100 MHz REFCLK with REFCLK Multiplier Bypassed
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
100kHz/
SPAN 1MHz
00
63
6-
01
2
Figure 13. Narrow-Band SFDR, 39.1 MHz, 1 MHz BW,
30 MHz REFCLK with REFCLK Multiplier = 10×
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5kHz/
SPAN 50kHz
00
63
6-
0
1
3
Figure 14. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
30 MHz REFCLK with REFCLK Multiplier = 10×
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5kHz/
SPAN 50kHz
006
36
-0
15
Figure 15. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
10 MHz REFCLK with REFCLK Multiplier = 10×
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| AD9856 | 制造商:AD 制造商全称:Analog Devices 功能描述:CMOS 200 MHz Quadrature Digital Upconverter |
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| AD9856ASTZ | 功能描述:IC UPCONVERTER DGTL QUAD 48TQFP RoHS:是 类别:RF/IF 和 RFID >> RF 其它 IC 和模块 系列:AD9856 标准包装:100 系列:* |
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