- 您现在的位置：买卖IC网 > PDF目录378276 > AD9878BST (ANALOG DEVICES INC) Mixed-Signal Front End for Broadband Applications PDF资料下载
参数资料
| 型号： | AD9878BST |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Mixed-Signal Front End for Broadband Applications |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封装： | MS-026BED, LQFP-100 |
| 文件页数： | 16/36页 |
| 文件大小： | 749K |
| 代理商： | AD9878BST |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页当前第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
AD9878
REGISTER 0x07—VIDEO INPUT CONFIGURATION
Bits [6:0]: Clamp Level Control Value
The 7-bit clamp-level control value is used to set an offset to the
automatic clamp-level control loop. The actual ADC output has a
clamp-level offset equal to 16 times the clamp level control value.
Rev. A | Page 16 of 36
( )
16
-
-
Value
Control
Level
Clamp
Offset
Level
Clamp
=
The default value for the clamp-level control value is 0x20. This
results in an ADC output clamp-level offset of 512 LSBs. The
valid programming range for the clamp-level control value is
0x16 to 0x127.
Bit 7: Video Input Enable
This bit enables the video input. In default with Bit 7 = 0, both
IF12 ADCs are connected to IF inputs. If the video input is
enabled by setting bit 7 = 1, the video input will be connected to
the IF12 ADC selected by REG 0x03, Bit 6.
REGISTER 0x08—ADC CLOCK CONFIGURATION
Bit 0: Send ADC12B Data Only
When this bit is set high, the device enters a nonmultiplexed
mode, and only the data from the ADC12B is sent to the
IF[11:0] digital output port.
Bit 1: Send ADC12A Data Only
When this bit is set high, the device enters a nonmultiplexed
mode, and only the data from the ADC12A is sent to the
IF[11:0] digital output port.
If both the send ADC12B data only and send ADC12A data
only register bits are set high, the device sends both ADC12A
and ADC12B data in the default multiplexed mode.
Bit 3: Power Down ADC10 Voltage Reference
Active high powers down the voltage reference circuit for
the ADC10.
Bit 4: Power Down RxSYNC Generator
Setting this bit to 1 powers down the 10-bit ADC’s sampling
clock and makes the RxSYNC output pin stay low. It can be
used for additional power saving on top of the power-down
selections in Register 0x02.
Bit 5: Rx PORT Fast Edge Rate
Setting this bit to 1 increases the output drive strength of all digital
output pins, except MCLK, REFCLK, SIGDELT, and
FLAG[2:1]. These pins always have high output drive capability.
Bit 7: ADC Clocked Directly from OSCIN
When set high, the ADC sampling clock is derived directly from
the input clock at OSCIN. In this mode, the clock supplied to the
OSCIN pin should originate from an external crystal or low jitter
crystal oscillator. When this bit is low, the ADC sampling clock
is derived from the internal PLL and the frequency of the clock
is equal to f
OSCIN
× M/8.
REGISTER 0x0C—DIE REVISION
Bits [3:0]: Version
The die version of the chip can be read from this register.
REGISTER 0x0D—Tx FREQUENCY TUNING WORDS
LSBs
This register accommodates the 2 LSBs for each frequency tuning
word (FTW). See the Registers 0x10 Through 0x17—
Burst Parameter section.
REGISTER 0x0E—DAC GAIN CONTROL
This register allows the user to program the DAC gain if the
Tx Gain Control Select Bit 3 in Register 0x0F is set to 0.
Table 5. DAC Gain Control
Bits [3:0]
0000
0001
0010
0011
…
1110
1111
DAC Gain (dB)
0.0 (default)
0.5
1.0
1.5
…
7.0
7.5
REGISTER 0x0F—Tx PATH CONFIGURATION
Bit 0: Single Tone Tx Mode
Active high configures the AD9878 for single-tone applications
(e.g., FSK). The AD9878 supplies a single frequency output, as
determined by the FTW selected by the active profile. In this
mode, the TxIQ input data pins are ignored, but should be tied
to a valid logic voltage level. Default value is 0x00 (inactive).
Bit 1: Spectral Inversion Tx
When set to 1, inverted modulation is performed:
[
_
I
OUT
MODULATOR
=
(
)
(
)
]
.
sin
cos
t
Q
t
ω
+
ω
Default is Logic 0, noninverted modulation:
(
)
(
)
[
]
.
sin
cos
_
t
Q
t
I
OUT
MODULATOR
ω
ω
=
Bit 2: Bypass Inv Sinc Tx Filter
Active high configures the AD9878 to bypass the sin(x)/x com-
pensation filter. Default value is 0x00 (inverse sinc filter enabled).
Bit 3: CA Interface Mode Select
This bit changes the format of the AD9878 3-wire CA interface to
a format in which the AD9878 digitally interfaces to external
variable gain amplifiers. This is accomplished by changing
the interpretation of the bits in Register 0x13, Register 0x17,
Register 0x1B, and Register 0x1F. See the Cable-Driver Gain
Control section for more detail.
相关PDF资料 |
PDF描述 |
|---|---|
| AD9878BSTZ | Mixed-Signal Front End for Broadband Applications |
| ADAV801 | Audio Codec for Recordable DVD |
| ADAV801ASTZ | Audio Codec for Recordable DVD |
| ADAV801ASTZ-REEL | Audio Codec for Recordable DVD |
| ADC0800PCD | ADC0800 8-Bit A/D Converter |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9878BSTRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 100-Pin LQFP T/R 制造商:Analog Devices 功能描述:MIXED SGNL FRONT END 100LQFP - Tape and Reel |
| AD9878BSTZ | 功能描述:IC FRONT-END MIXED-SGNL 100-LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD9878-EB | 制造商:Analog Devices 功能描述:EVAL KIT FOR MIXED-SGNL FRONT END FOR BROADBAND APPLICATIONS - Bulk |
| AD9879 | 制造商:AD 制造商全称:Analog Devices 功能描述:Mixed-Signal Front End Set-Top Box, Cable Modem |
| AD9879_05 | 制造商:AD 制造商全称:Analog Devices 功能描述:Mixed-Signal Front End Set-Top Box, Cable Modem |
发布紧急采购，3分钟左右您将得到回复。