参数资料
型号: AD9878BST
厂商: ANALOG DEVICES INC
元件分类: 通信及网络
英文描述: Mixed-Signal Front End for Broadband Applications
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP100
封装: MS-026BED, LQFP-100
文件页数: 20/36页
文件大小: 749K
代理商: AD9878BST
AD9878
THEORY OF OPERATION
For a general understanding of the AD9878, refer to Figure 23, a
block diagram of the device architecture. The device consists of a
transmit path, receive path, and auxiliary functions, such as a PLL,
a ∑- DAC, a serial control port, and a cable amplifier interface.
Rev. A | Page 20 of 36
The transmit path contains an interpolation filter, a complete
quadrature digital upconverter, an inverse sinc filter, and a 12-bit
current output DAC.
The receive path contains a 10-bit ADC and dual 12-bit ADCs.
All internally required clocks and an output system clock are
generated by the PLL from a single crystal or clock input.
The 12-bit and 10-bit IF ADCs can convert direct IF inputs of
up to 70 MHz and run at sample rates of up to 29 MSPS. A video
input with an adjustable signal clamping level, along with the
10-bit ADC, allow the AD9878 to process an NTSC and a QAM
channel simultaneously.
The programmable ∑- DAC can be used to control external
components, such as variable gain amplifiers (VGAs) or voltage-
controlled tuners. The CA port provides an interface to the
AD832x family of programmable gain amplifier (PGA) cable
drivers, enabling host processor control via the MxFE serial
port (SPORT).
0
TxIQ[5:0]
TxSYNC
MCLK
REFCLK
CA PORT
PROFILE
SDIO
IF10[4:0]
RxSYNC
IF12[11:0]
FSADJ
XTAL
OSCIN
Σ
-
OUTPUT
FLAG[2:1]
IF10 INPUT
IF12B INPUT
VIDEO IN
6
3
12
12
12
AD9878
DATA
ASSEMBLER
QUADRATURE
MODULATOR
FIR LPF
CIC LPF
COS
SIN
DAC GAIN CONTROL
PLL
OSCIN
×
M
DDS
MUX
MUX
CA
INTERFACE
PROFILE
SELECT
SERIAL
INTERFACE
12
4
SINC
–1
MUX
DAC
IF10
IF12
ADC
ADC
10
12
12
4
5
5
12
12
I
Q
Rx PORT
Tx OUTPUT
Σ
-
INPUT
4
4
4
8
FLAG0
SINC
–1
BYPASS
(
f
OSCIN
)
(
f
OSCIN
)
(
f
MCLK
)
MUX
12
ADC
MUX
IF12A INPUT
DAC
+
CLAMP LEVEL
Σ
-
÷
R
÷
8
÷
2
÷
2
(
f
IQCLK
)
(
f
SYSCLK
)
(
f
OSCIN
)
÷
4
÷
4
Figure 23. AD9878 Block Diagram
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