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| 型号： | AD9888KSZ-140 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/36页 |
| 文件大小： | 0K |
| 描述： | IC FLAT PANEL INTERFACE 128-MQFP |
| 标准包装： | 1 |
| 应用： | 图形卡，VGA 接口 |
| 接口： | 2 线串口 |
| 电源电压： | 3 V ~ 3.6 V |
| 封装/外壳： | 128-BFQFP |
| 供应商设备封装： | 128-MQFP（14x20） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
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AD9888
Data Sheet
Rev. C | Page 24 of 36
2-WIRE SERIAL CONTROL REGISTER DETAILS
CHIP IDENTIFICATION
Address 0x00[7:0]—Chip Revision
An 8-bit register that represents the silicon revision.
PLL DIVIDER CONTROL
Address 0x01[7:0]—PLL Divide Ratio MSBs
The eight MSBs of the 12-bit PLL divide ratio (PLLDIV). The
operational divide ratio is PLLDIV + 1.
The PLL derives a master clock from an incoming HSYNC signal.
The master clock frequency is then divided by an integer value,
such that the output is phase locked to HSYNC. This PLLDIV
value determines the number of pixel times (pixels plus horizontal
blanking overhead) per line. This is typically 20% to 30% more
than the number of active pixels in the display.
The 12-bit value of the PLL divider supports divide ratios from
2 to 4095. The higher the value loaded in this register, the higher
the resulting clock frequency with respect to a fixed HSYNC
frequency.
VESA has established standard timing specifications that assist in
determining the value for PLLDIV as a function of horizontal and
vertical display resolution and frame rate (see Table 5). However,
many computer systems do not conform precisely to the recom-
mendations, and these numbers should be used only as a guide.
The display system manufacturer should provide automatic or
manual means for optimizing PLLDIV. An incorrectly set PLLDIV
usually produces one or more vertical noise bars on the display.
The greater the error, the greater the number of bars produced.
The power-up default value of PLLDIV is 1693 (PLLDIVM = 0x69,
PLLDIVL = 0xDx).
The AD9888 updates the full divide ratio only when the LSBs are
changed. Writing to this register by itself does not trigger an update.
Address 0x02[7:4]—PLL Divide Ratio LSBs
The four LSBs of the 12-bit PLL divide ratio (PLLDIV). The
operational divide ratio is PLLDIV + 1.
The power-up default value of PLLDIV is 1693 (PLLDIVM = 0x69,
PLLDIVL = 0xDx).
The AD9888 updates the full divide ratio only when this register is
written to.
CLOCK GENERATOR CONTROL
Address 0x03[7:6]—VCO Range Select
Two bits that establish the operating range of the clock generator.
The VCO range must be set to correspond with the desired
operating frequency (incoming pixel rate).
The PLL provides the best jitter performance at high frequencies.
To output low pixel rates while minimizing jitter, the PLL operates
at a higher frequency and then divides down the clock rate after-
wards. Table 9 shows the pixel rates for each VCO range setting.
The PLL output divisor is automatically selected with the VCO
range setting.
Table 9. VCO Ranges Settings
VCO Range Select Setting
Data Clock Range (MHz)
00
10 to 41
01 (default)
41 to 82
10
82 to 150
11
150+
Address 0x03[5:3]—Charge Pump Current
Three bits that establish the current driving the loop filter in the
clock generator. These bits must be set to correspond with the
desired operating frequency (incoming pixel rate).
Table 10. Charge Pump Current Settings
Charge Pump Current Setting
Current (mA)
000
50
001 (default)
100
010
150
011
250
100
350
101
500
110
750
111
1500
Address 0x04[7:3]—Clock Phase Adjust
A 5-bit value that adjusts the sampling phase in 32 steps across one
pixel time. Each step represents an 11.25° shift in sampling phase.
The power-up default value is 16.
CLAMP TIMING
Address 0x05[7:0]—Clamp Placement
An 8-bit register that sets the position of the internally
generated clamp.
When the external clamp control bit is set to 0, a CLAMP signal is
generated internally after the trailing edge of HSYNC at a position
(in pixel periods) established by the clamp placement bits and
for a duration (in pixel periods) set by the clamp duration bits.
The clamp placement can be programmed to any value up to
255, except 0.
The clamp should be placed during a time when the input
signal presents a stable black level reference, usually the back
porch period between HSYNC and the image.
When the external clamp control bit is set to 1, this register is
ignored.
Address 0x06[7:0]—Clamp Duration
An 8-bit register that sets the duration of the internally
generated clamp.
When the external clamp control bit is set to 0, a CLAMP signal is
generated internally after the trailing edge of HSYNC at a position
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相关代理商/技术参数 |
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| AD9888KSZ-140 | 制造商:Analog Devices 功能描述:IC ANALOG INTERFACE |
| AD9888KSZ-170 | 功能描述:IC ANALOG INTRFC 170MSPS 128MQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD9888KSZ-170 | 制造商:Analog Devices 功能描述:TV / Video IC |
| AD9888KSZ-205 | 制造商:Analog Devices 功能描述:205MHZ ANALOG GRAPHICS INTERFACE 制造商:Analog Devices 功能描述:IC ANALOG INTERFACE |
| AD9888KSZ-205KL1 | 制造商:Analog Devices 功能描述:- Rail/Tube |
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