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参数资料
| 型号： | AD9888KSZ-140 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/36页 |
| 文件大小： | 0K |
| 描述： | IC FLAT PANEL INTERFACE 128-MQFP |
| 标准包装： | 1 |
| 应用： | 图形卡，VGA 接口 |
| 接口： | 2 线串口 |
| 电源电压： | 3 V ~ 3.6 V |
| 封装/外壳： | 128-BFQFP |
| 供应商设备封装： | 128-MQFP（14x20） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
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AD9888
Data Sheet
Rev. C | Page 12 of 36
DESIGN GUIDE
GENERAL DESCRIPTION
The AD9888 is a fully integrated solution for capturing analog
RGB signals and digitizing them for display on flat panel monitors
or projectors. The circuit is ideal for providing a computer interface
for HDTV monitors or for serving as the front end of high perfor-
mance video scan converters.
Implemented in a high performance CMOS process, the interface
can capture signals with pixel rates of up to 170 MHz, or of up
to 340 MHz with an alternate pixel sampling mode.
The AD9888 includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control, and
output data formatting. All controls are programmable via a
2-wire serial interface. Full integration of these sensitive analog
functions makes system design straightforward and less sensitive to
the physical and electrical environment.
With a typical power dissipation of only 920 mW and an operating
temperature range of 0°C to 70°C, the device requires no special
environmental considerations.
INPUT SIGNAL HANDLING
The AD9888 has six high impedance analog input pins for the
red, green, and blue channels. They accommodate signals ranging
from 0.5 V p-p to 1.0 V p-p.
Signals are typically brought onto the interface board via a
digital visual interface integrated (DVI-I) connector, a 15-pin
D connector, or BNC connectors. The AD9888 should be
located as close as possible (or as close as is practical) to the
input connector. Signals should be routed via matched
impedance traces (normally 75 Ω) to the IC input pins.
At this point, the signal should be resistively terminated (to the
signal ground return) and capacitively coupled to the AD9888
inputs through 47 nF capacitors. These capacitors form part of
the dc restoration circuit.
If it were possible to have perfectly matched impedances, the
best performance would be obtained with the widest possible
signal bandwidth. The ultrawide bandwidth inputs of the
AD9888 (500 MHz) would track the input signal continuously
as it moved from one pixel level to the next, and then digitize
the pixel during a long, flat pixel time. In real-world conditions,
however, there are mismatches, reflections, and noise, which
can result in excessive ringing and distortion of the input
waveform. This makes it more difficult to establish a sampling
phase that provides good image quality. The AD9888 can
digitize graphics signals over a very wide range of frequencies
(10 MHz to 170 MHz). Often, characteristics that are beneficial
at one frequency can be detrimental at another. Analog
bandwidth is one such characteristic. For UXGA resolutions
(up to 170 MHz), a very high analog bandwidth is desirable
because of the fast input signal slew rates. For VGA and lower
resolutions (down to 12.5 MHz), a very high bandwidth is not
desirable because it allows excess noise to pass through. To
accommodate these varying needs, the AD9888 includes a
variable analog bandwidth control. Four settings are available
(75 MHz, 150 MHz, 300 MHz, and 500 MHz), allowing the
analog bandwidth to be matched with the resolution of the
incoming graphics signal.
RGB
INPUT
RAIN
GAIN
BAIN
47nF
75
02442
-00
3
Figure 4. Analog Input Interface Circuit
SYNC PROCESSING OVERVIEW
The AD9888 circuitry enables it to accept composite sync
inputs, such as sync-on-green or the trilevel sync inputs found
in digital TV signals. A complete description of the sync
processing functionality is found in the Sync Slicer and the Sync
Separator sections.
HSYNC AND VSYNC INPUTS
The interface can also accept a horizontal sync signal, which is
used to generate the pixel clock and clamp timing. It is possible
to operate the AD9888 without applying HSYNC (that is, by
using an external clock, external clamp, and single port output
mode), but a number of features of the chip will be unavailable;
therefore, it is recommended that HSYNC be provided. This
can be either a sync signal directly from the graphics source or a
preprocessed TTL- or CMOS-level signal.
The HSYNC input includes a Schmitt-trigger buffer for
immunity to noise and signals with long rise times. In typical
PC-based graphics systems, the sync signals are simply TTL-
level drivers feeding unshielded wires in the monitor cable.
Therefore, no termination is required or desired.
SERIAL CONTROL PORT
The serial control port is designed for 3.3 V logic. If there are
5 V drivers on the bus, these pins should be protected with
150 Ω series resistors placed between the pull-up resistors and
the input pins.
OUTPUT SIGNAL HANDLING
The digital outputs are designed and specified to operate from a
3.3 V power supply (VDD). They can also work with a VDD as low
as 2.5 V for compatibility with other 2.5 V logic.
CLAMPING
RGB Clamping
To digitize the incoming signal properly, the dc offset of the
input must be adjusted to fit the range of the on-board ADCs.
Most graphics systems produce RGB signals with black at
ground and white at approximately 0.75 V. However, if sync
signals are embedded in the graphics, the sync tip is often at
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| AD9888KSZ-140 | 制造商:Analog Devices 功能描述:IC ANALOG INTERFACE |
| AD9888KSZ-170 | 功能描述:IC ANALOG INTRFC 170MSPS 128MQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD9888KSZ-170 | 制造商:Analog Devices 功能描述:TV / Video IC |
| AD9888KSZ-205 | 制造商:Analog Devices 功能描述:205MHZ ANALOG GRAPHICS INTERFACE 制造商:Analog Devices 功能描述:IC ANALOG INTERFACE |
| AD9888KSZ-205KL1 | 制造商:Analog Devices 功能描述:- Rail/Tube |
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