参数资料
型号: AD9888KSZ-140
厂商: Analog Devices Inc
文件页数: 21/36页
文件大小: 0K
描述: IC FLAT PANEL INTERFACE 128-MQFP
标准包装: 1
应用: 图形卡,VGA 接口
接口: 2 线串口
电源电压: 3 V ~ 3.6 V
封装/外壳: 128-BFQFP
供应商设备封装: 128-MQFP(14x20)
包装: 托盘
安装类型: 表面贴装
AD9888
Data Sheet
Rev. C | Page 28 of 36
Address 0x14[7]—HSYNC Detect
This bit indicates when activity is detected on the selected
HSYNC input pin. If HSYNC is held high or low, activity is not
detected.
Table 28. HSYNC Detection Results
HSYNC Detect Setting
Function
0
No activity detected
1
Activity detected
The sync processing block diagram (Figure 27) shows where
this function is implemented.
Address 0x14[6]—Active HSYNC (AHS)
This bit indicates which horizontal sync input source (HSYNC
or SOG) is used by the PLL (see Table 29). When AHS is 0, the
HSYNC pin is used. When AHS is 1, the SOG pin is used.
Determine which source is active by using Bit 7 and Bit 1 in this
register. Bit 7 indicates when activity is detected on HSYNC,
and Bit 1 indicates when activity is detected on SOG. If activity
is detected on both HSYNC and SOG, the user can determine
which has priority via Bit 3 in Register 0x0E. The user can
override the function of AHS via Bit 4 in Register 0x0E. If the
override bit is set to Logic 1, AHS is forced to the state that Bit 3
is set to in Register 0x0E.
Table 29. Active HSYNC Settings
Active HSYNC Setting
Function
1
SOG pin is used for HSYNC input
0
HSYNC pin is used for HSYNC input
Table 30. Active HSYNC Results
Bit 7 in 0x14
(HSYNC Detect)
Bit 1 in 0x14
(SOG Detect)
Bit 4 in 0x0E
(Override)
AHS
0
N/A (use
Bit 3 in 0x0E)
0
1
0
1
0
1
0
N/A (use
Bit 3 in 0x0E)
X1
1
N/A (use
Bit 3 in 0x0E)
1 X = don’t care.
Address 0x14[5]—Detected HSYNC Input Polarity Status
This bit reports the status of the HSYNC input polarity detection
circuit. It can be used to determine the polarity of the HSYNC
input. The location of the detection circuit is shown in the sync
processing block diagram (Figure 27).
Table 31. Detected HSYNC Input Polarity Status
Detected HSYNC Input Polarity
Status Setting
Function
0
HSYNC polarity is negative.
1
HSYNC polarity is positive.
Address 0x14[4]—VSYNC Detect
This bit is used to indicate when activity is detected on the
selected VSYNC input pin. If VSYNC is held high or low,
activity is not detected.
Table 32. VSYNC Detection Status
VSYNC Detect Setting
Function
0
No activity detected
1
Activity detected
The sync processing block diagram (Figure 27) shows where
this function is implemented.
Address 0x14[3]—Active VSYNC (AVS)
This bit indicates which VSYNC source is being used: the
VSYNC input or the output from the sync separator. When AVS
is 1, the sync separator is used. When AVS is 0, the VSYNC
input is used.
Determine which source is active by using Bit 4 and Bit 1 in this
register. Bit 4 indicates when activity is detected on VSYNC,
and Bit 1 indicates when activity is detected on SOG. If activity
is detected on both VSYNC and SOG, the user can determine
which has priority via Bit 0 in Register 0x0E. The user can
override the function of AVS via Bit 1 in Register 0x0E. If the
override bit is set to Logic 1, AVS is forced to the state that Bit 0
is set to in Register 0x0E.
Table 33. Active VSYNC Settings
Active VSYNC Setting
Function
1
The sync separator is used
0
The VSYNC input is used
Table 34. Active VSYNC Results
Bit 4 in 0x14
(VSYNC Detect)
Bit 1 in 0x14
(SOG Detect)
Bit 1 in 0x0E
(Override)
AVS
0
1
0
1
N/A (use
Bit 0 in 0x0E)
1 X = don’t care.
Address 0x14[2]—Detected VSYNC Output Polarity
Status
This bit indicates the status of the VSYNC output polarity
detection circuit and can be used to determine the polarity of
the VSYNC input. The location of the detection circuit is shown
in the sync processing block diagram (Figure 27).
Table 35. Detected VSYNC Input Polarity Status
Detected VSYNC Output Polarity
Status Setting
Function
0
VSYNC polarity is active
high.
1
VSYNC polarity is active
low.
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