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参数资料
| 型号： | AD9888KSZ-140 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/36页 |
| 文件大小： | 0K |
| 描述： | IC FLAT PANEL INTERFACE 128-MQFP |
| 标准包装： | 1 |
| 应用： | 图形卡，VGA 接口 |
| 接口： | 2 线串口 |
| 电源电压： | 3 V ~ 3.6 V |
| 封装/外壳： | 128-BFQFP |
| 供应商设备封装： | 128-MQFP（14x20） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
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Data Sheet
AD9888
Rev. C | Page 25 of 36
(in pixel periods) established by the clamp placement bits and
for a duration (in pixel periods) set by the clamp duration bits.
The clamp duration can be programmed to any value between 1
and 255. A value of 0 is not supported.
For the best results, the clamp duration should be set to include
the majority of the black reference signal time that follows the
HSYNC signal trailing edge. Insufficient clamping time can
produce brightness changes at the top of the screen and a slow
recovery from large changes in the average picture level (APL),
or brightness.
When the external clamp control bit is set to 1, this register is
ignored.
HSYNC PULSE WIDTH
Address 0x07[7:0]—HSYNC Output Pulse Width
An 8-bit register that sets the duration of the HSYNC output pulse.
The leading edge of the HSYNC output is triggered by the
internally generated, phase-adjusted PLL feedback clock. The
AD9888 then counts a number of pixel clocks equal to the value
in this register. This triggers the trailing edge of the HSYNC
output, which is also phase adjusted.
INPUT GAIN
Address 0x08[7:0]—Red Channel Gain Adjust (Red Gain)
An 8-bit word that sets the gain of the red channel.
The AD9888 can accommodate input signals with a full-scale range
between 0.5 V p-p and 1.0 V p-p. Setting red gain to 255 corres-
ponds to an input range of 1.0 V p-p. A red gain of 0 establishes
an input range of 0.5 V p-p. Note that increasing red gain results
in the picture having less contrast because the input signal uses
fewer of the available converter codes (see Figure 5). The same
functionality also applies to the green and blue channel gain
adjust bits.
Address 0x09[7:0]—Green Channel Gain Adjust
(Green Gain)
An 8-bit word that sets the gain of the green channel (see the
section for more information).
Address 0x0A[7:0]—Blue Channel Gain Adjust (Blue Gain)
An 8-bit word that sets the gain of the blue channel (see the
section for more information).
INPUT OFFSET
Address 0x0B[7:1]—Red Channel Offset Adjust
(Red Offset)
A 7-bit offset binary word that sets the dc offset of the red channel.
One LSB of offset adjustment equals approximately one LSB change
in the ADC offset. Therefore, the absolute magnitude of the offset
adjustment scales as the gain of the channel changes. A nominal
setting of 63 results in the channel nominally clamping to Code 00
during the back porch clamping interval. An offset setting of 127
results in the channel clamping to Code 64 of the ADC. An offset
setting of 0 clamps to Code 63. Increasing the value of red
offset decreases the brightness of the channel. The same
functionality also applies to the green and blue channel offset
adjust bits.
Address 0x0C[7:1]—Green Channel Offset Adjust
(Green Offset)
A 7-bit offset binary word that sets the dc offset of the green
channel (see the Address 0x0B[7:1]—Red Channel Offset
Adjust (Red Offset) section for more information).
Address 0x0D[7:1]—Blue Channel Offset Adjust
(Blue Offset)
A 7-bit offset binary word that sets the dc offset of the blue
channel (see the Address 0x0B[7:1]—Red Channel Offset
Adjust (Red Offset) section for more information).
SYNC CONTROL
Address 0x0E[7]—HSYNC Input Polarity Override
This register is used to override the internal circuitry that
determines the polarity of the HSYNC signal going into the PLL.
Table 11. HSYNC Input Polarity Override Settings
HSYNC Input Polarity
Override Setting
Function
0 (default)
HSYNC polarity is determined by chip.
1
HSYNC polarity is determined by user.
Address 0x0E[6]—HSYNC Input Polarity
This bit must be set to indicate the polarity of the HSYNC
signal that is applied to the PLL HSYNC input.
Table 12. HSYNC Input Polarity Settings
HSYNC Input Polarity
Setting
Function
0
Active low
1 (default)
Active high
Active low means that the leading edge of the HSYNC pulse is
negative-going and, therefore, timing is based on the leading
edge of HSYNC, which is the falling edge. The rising edge has
no effect.
Active high means that the leading edge of the HSYNC pulse is
positive-going and, therefore, timing is based on the leading
edge of HSYNC, which is the rising edge.
Although the device can operate if this bit is set incorrectly, the
internally generated clamp position, as established by the clamp
placement (Register 0x05), will not be placed as expected, which
may generate clamping errors.
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相关代理商/技术参数 |
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| AD9888KSZ-140 | 制造商:Analog Devices 功能描述:IC ANALOG INTERFACE |
| AD9888KSZ-170 | 功能描述:IC ANALOG INTRFC 170MSPS 128MQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD9888KSZ-170 | 制造商:Analog Devices 功能描述:TV / Video IC |
| AD9888KSZ-205 | 制造商:Analog Devices 功能描述:205MHZ ANALOG GRAPHICS INTERFACE 制造商:Analog Devices 功能描述:IC ANALOG INTERFACE |
| AD9888KSZ-205KL1 | 制造商:Analog Devices 功能描述:- Rail/Tube |
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