参数资料
型号: AD9912ABCPZ-REEL7
厂商: Analog Devices Inc
文件页数: 7/40页
文件大小: 0K
描述: IC DDS 1GSPS DAC 14BIT 64LFCSP
产品培训模块: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
标准包装: 750
分辨率(位): 14 b
主 fclk: 1GHz
调节字宽(位): 48 b
电源电压: 1.8V, 3.3V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘,CSP
供应商设备封装: 64-LFCSP-VQ(9x9)
包装: 带卷 (TR)
AD9912
Rev. F | Page 15 of 40
06
76
3-
0
21
0
200
400
600
800
FREQUENCY (MHz)
650
600
550
500
450
A
M
PL
IT
U
D
E
(mV)
NOM SKEW 25°C, 1.8V SUPPLY
WORST CASE (SLOW SKEW 90°C, 1.7V SUPPLY)
06
76
3-
0
24
0
0.5
1.0
1.5
2.0
2.5
TIME (ns)
0.4
0.6
0.2
0
–0.2
–0.4
–0.6
AM
P
L
IT
UD
E
(
V
)
FREQUENCY = 600MHz
tRISE (20%→80%) = 104ps
tFALL (80%→20%) = 107ps
V p-p = 1.17V DIFF.
DUTY CYCLE = 50%
Figure 27. HSTL Output Driver Single-Ended Peak-to-Peak Amplitude vs.
Toggle Rate (100 Ω Across Differential Pair)
Figure 30. Typical HSTL Output Waveform, Nominal Conditions,
DC-Coupled, Differential Probe Across 100 Ω load
06
76
3-
0
22
0
1020
304
FREQUENCY (MHz)
2.5
2.0
1.5
1.0
0.5
0
AM
P
L
IT
UDE
(
V
)
06
76
3-
0
25
0
20
40
60
80
100
TIME (ns)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
AM
P
L
IT
U
DE
(
V
)
FREQUENCY = 20MHz
tRISE (20%→80%) = 5.5ns
tFALL (80%→20%) = 5.9ns
V p-p = 1.8V
DUTY CYCLE = 53%
0
NOM SKEW 25°C, 1.8V SUPPLY (20pF)
WORST CASE (SLOW SKEW 90°C,
1.7V SUPPLY (20pF))
Figure 31. Typical CMOS Output Driver Waveform (@ 1.8 V),
Nominal Conditions, Estimated Capacitance = 5 pF
Figure 28. CMOS Output Driver Peak-to-Peak Amplitude vs. Toggle Rate
(AVDD3 = 1.8 V) with 20 pF Load
06
76
3-
0
23
0
50
100
150
FREQUENCY (MHz)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
AM
P
L
IT
UDE
(
V
)
NOM SKEW 25°C, 1.8V SUPPLY (20pF)
WORST CASE (SLOW SKEW 90°C,
3.0V SUPPLY (20pF))
06
76
3-
0
26
0
10
2030
405
TIME (ns)
3.3
2.8
2.3
1.8
1.3
0.8
0.3
–0.2
0
AM
P
L
IT
UD
E
(
V
)
FREQUENCY = 40MHz
tRISE (20%→80%) = 2.25ns
tFALL (80%→20%) = 2.6ns
V p-p = 3.3V
DUTY CYCLE = 52%
Figure 32. CMOS Output Driver Waveform (@ 3.3 V),
Nominal Conditions, Estimated Capacitance = 5 pF
Figure 29. CMOS Output Driver Peak-to-Peak Amplitude vs. Toggle Rate
(AVDD3 = 3.3 V) with 20 pF Load
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