- 您现在的位置：买卖IC网 > PDF目录10979 > AD9913BCPZ (Analog Devices Inc)IC DDS 10BIT DAC 250MSPS 32LFCSP PDF资料下载
参数资料
| 型号： | AD9913BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/32页 |
| 文件大小： | 0K |
| 描述： | IC DDS 10BIT DAC 250MSPS 32LFCSP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 250MHz |
| 调节字宽（位）： | 32 b |
| 电源电压： | 1.8V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 托盘 |
| 产品目录页面： | 552 (CN2011-ZH PDF) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页当前第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页
AD9913
Rev. A | Page 19 of 32
is to reset digital logic in the PLL circuit with an active low
signal. The function of CFR2 [5] is to power up or power down
the PLL.
CFR2 [4] is the PLL LO range bit. When operating the AD9913
with the PLL enabled, CFR2 [4] adjusts PLL loop filter
components to allow low frequency reference clock inputs.
CFR2 [3] enables a divide-by-two circuit at the input of the PLL
phase detector. If this bit is enabled the reference clock signal is
divided by 2 prior to multiplication in the PLL. Refer to the
electrical specifications for the maximum reference clock input
frequency when utilizing the PLL with the divide by 2 circuit
enabled. If the divide by 2 circuit is disabled and the PLL is
enabled, then the maximum reference clock input frequency is
one-half the maximum rate indicated in the electrical
specifications table for the maximum input divider frequency.
The AD9913 PLL uses one of two VCOs for producing the
system clock signal. CFR2 Bit 2 is a select bit that enables an
alternative VCO in the PLL. The basic operation of the PLL is
not affected by the state of this bit. The purpose of offering two
VCOs is to provide performance options. The two VCOs have
approximately the same gain characteristics, but differ in other
aspects. The overall spurious performance, phase noise, and
power consumption may change based on the setting of CFR2
Bit 2. It is important to consider that for either VCO, the
minimum oscillation frequency must be satisfied, and that
minimum oscillation frequency is significantly different
between the two oscillators.
CFR2 [15:9], along with CFR2 [3], determine the multiplication
of the PLL. CFR2 [15] enables a divider at the output of the
PLL. The bits CFR [14:9] control the feedback divider. The
feedback divider is composed of two stages: ÷ N (1:31) selected
by CFR2 [13:9]; ÷1 or ÷2 selected by CFR2 [14].
Note that the same system clock frequency can be obtained with
different combinations of CFR2 [15:9] and CFR2 [3]. One
combination may work better in a given application either to
run at lower power or to satisfy the VCOs minimum oscillation
frequency
Note that the AD9913 maximum system clock frequency is
250 MHz. If the user intends to use high values for the PLL
feedback divider ratio, then care should be taken that the
system clock frequency does not exceed 250 MHz.
PLL LOCK INDICATION
CFR2 [0] is a read-only bit that displays the status of the PLL
lock signal.
When the AD9913 is programmed to use the PLL, there is some
amount of time required for the loop to lock. While the loop is
not locked, the chip system clock operates at the reference clock
frequency presented to the part at the pins. Once the PLL lock
signal goes high, the system clock frequency switches
asynchronously to operate at the PLL output frequency. To
maintain a system clock frequency with or without a locked
loop if the PLL lock signal transistions low, the chip reverts to
the reference clock signal while the loop attempts to acquire
lock once again.
Table 7 describes how to configure the PLL multiplication factor
using the appropriated register bits.
相关PDF资料 |
PDF描述 |
|---|---|
| MCF51JE128CMB | IC MCU 128K COLDF 81-PBGA |
| AD5930YRUZ | IC GEN PROG FREQ BURST 20TSSOP |
| S9S12HY64J0MLL | MCU 64K FLASH AUTO 100-LQFP |
| VI-21K-CU-S | CONVERTER MOD DC/DC 40V 200W |
| VI-21J-CU-S | CONVERTER MOD DC/DC 36V 200W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9913BCPZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
| AD9913BCPZ-REEL7 | 功能描述:IC DDS 250MSPS 10BIT ADC 32LFCSP RoHS:是 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| AD9913BCPZ-REEL71 | 制造商:AD 制造商全称:Analog Devices 功能描述:Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
| AD9914 | 制造商:AD 制造商全称:Analog Devices 功能描述:3.5 GSPS Direct Digital Synthesizer with 12-Bit DAC |
| AD9914/PCBZ | 功能描述:数据转换 IC 开发工具 3.5 GSPS DDS w/Upconverter eval bd. RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
发布紧急采购，3分钟左右您将得到回复。