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| 型号： | AD9913BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/32页 |
| 文件大小： | 0K |
| 描述： | IC DDS 10BIT DAC 250MSPS 32LFCSP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 250MHz |
| 调节字宽（位）： | 32 b |
| 电源电压： | 1.8V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 托盘 |
| 产品目录页面： | 552 (CN2011-ZH PDF) |
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AD9913
Rev. A | Page 15 of 32
Table 5. Determining the Direction of the Linear Sweep
Profile Pins [2:0] or CFR1 Bits [22:20]
Linear Sweep Mode
Sweep off
For a piecemeal or a nonlinear transition between S0 and E0,
the delta tuning words and ramp rate words can be reprogram-
med during the transition.
Ramp up
Ramp down
The formulas for calculating the step size of RDW or FDW are
Bidirectional ramp
SYSCLK
f
RDW
Step
Frequency
=
32
2
(MHz)
1 x = don’t care.
π
=
13
2
RDW
Step
Phase
(radians)
Note that if the part is used in parallel port programming mode,
the sweep mode is only determined by the internal profile
control bits, CFR1 [22:20]. If the part is used in serial port
programming mode, either the internal profile control bits or
the external profile select pins can work as the sweep control.
CFR1 [27] selects between these two approaches.
=
11
2
45RDW
Step
Phase
(degrees)
The formula for calculating delta time from RSRR or FSRR is
(
)
(Hz)
/
SYSCLK
f
RSRR
t =
Δ
Setting the Slope of the Linear Sweep
The slope of the linear sweep is set by the intermediate step size
(delta tuning word) between S0 and E0 (see Figure 22) and the
time spent (sweep ramp rate word) at each step. The resolution
of the delta tuning word is 32 bits for frequency and 14 bits for
phase. The resolution for the delta ramp rate word is 16 bits.
At 250 MSPS operation, (fSYSCLK =250 MHz). The minimum time
interval between steps is 1/250 MHz × 1 = 4 ns. The maximum
time interval is (1/250 MHz) × 65,535= 262 μs.
Frequency Linear Sweep Example
In linear sweep mode, when sweeping from low to high, the
RDW is applied to the input of the auxiliary accumulator and
the RSRR register is loaded into the sweep rate timer.
In linear sweep mode, the user programs a rising delta word
(RDW, Register 0x07) and a rising sweep ramp rate (RSRR,
Register 0x08). These settings apply when sweeping from S0 to
E0. The falling delta word (FDW, Register 0x07) and falling
sweep ramp rate (FSRR, Register 0x08) apply when sweeping
from E0 to S0.
The RDW accumulates at the rate given by the ramp rate
(RSRR) until the output equals the upper limit in the linear
sweep parameter register (Register 0x06). The sweep is then
complete.
Note that if the auxiliary accumulator is allowed to overflow, an
uncontrolled, continuous sweep operation occurs. To avoid this,
the magnitude of the rising or falling delta word should be
smaller than the difference between full-scale and the E0 value
(full-scale E0). For a frequency sweep, full-scale is 232 1. For
a phase sweep, full-scale is 214 1.
When sweeping from high to low, the FDW is applied to the
input of the auxiliary accumulator and the FSRR register is
loaded into the sweep rate timer.
The FDW accumulates at the rate given by the ramp rate
(FSRR) until the output equals the lower limit in the linear
sweep parameter register value (Register 0x06). The sweep is
then complete. A phase sweep works in the same manner with
fewer bits.
Figure 22 displays a linear sweep up and then down. This
depicts the dwell mode (see CRF1 [8]). If the no-dwell bit,
CFR1 [8], is set, the sweep accumulator returns to 0 upon
reaching E0.
To view sweep capabilities using the profile pins and the no-
S0
E0
TIME
RDW
FDW
RSRR
FSRR
L
INE
AR
S
W
E
P
(F
RE
Q
UE
NCY
/P
HAS
E
)
Δf, p
Δt
07
00
2-
0
37
Figure 22. Linear Sweep Mode
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