参数资料
型号: AD9953YSVZ
厂商: Analog Devices Inc
文件页数: 11/32页
文件大小: 0K
描述: IC DDS DAC 14BIT 400MSPS 48-TQFP
产品培训模块: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
标准包装: 1
分辨率(位): 14 b
主 fclk: 400MHz
调节字宽(位): 32 b
电源电压: 1.71 V ~ 1.96 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 48-TQFP 裸露焊盘
供应商设备封装: 48-TQFP 裸露焊盘(7x7)
包装: 托盘
产品目录页面: 552 (CN2011-ZH PDF)
AD9953
Rev. A | Page 19 of 32
s 0x05)
put
W
ent
M,
s
.
ct pins PS<1:0>.
ial
to the ending address.
e the serial port to expect
bit words. The first 32 bits would be parsed as a word
ed
n).
ase
r.
-tone FSK, the user programs each RAM segment
or
e adder (<31:18>).
s
dest
irect
it
m
odes that enable the memory,
bit controls whether the RAM output
ulator or the phase offset adder.
r finishes a cycle, the RAM address generator
crements to the next address and the timer reloads the ramp
te bits and begins a new countdown cycle. This sequence
ontinues until the RAM address generator has incremented to
n address equal to the RAM segment final address bits of the
urrent RSCW.
input of the phase accumulator and supplies the frequency
tuning word(s) for the device. When the RAM output drives the
phase accumulator, the phase offset word (POW, Addres
drives the phase-offset adder. Similarly, when the RAM out
,
drives the phase offset adder, the frequency tuning word (FT
Address 0x04) drives the phase accumulator. When CFR1<31>
is Logic 0, the RAM is inactive unless being written to via the
serial port. The power-up state of the AD9953 is the single-tone
mode, in which the RAM enable bit is inactive. The RAM is
segmented into four unique slices controlled by the Profile<1:0
input pins.
rolled
>
RAM Controlled Modes of Operation
Direct Switch Mode
Direct switch mode enables FSK or PSK modulation. The
AD9953 is programmed for direct switch mode by writing the
RAM enable bit true and programming the RAM segment
mode control bits of each desired profile to Logic 000(b). This
mode simply reads the RAM contents at the RAM segment
beginning address for the current profile. No address ramping is
enabled in direct switch mode.
To perform 4
All RAM writes/reads, unless otherwise specified, are cont
by the Profile<1:0> input pins and the respective RAM segm
control word. The RAM can be written to during normal
operation, but any I/O operation that commands the RAM to be
written immediately suspends read operation from the RA
causing the current mode of operation to be nonfunctional. Thi
excludes single-tone mode, as the RAM is not read in this mode
Writing the RAM is accomplished as follows. After configuring
the desired RAM segment control words, the desired RAM
c
segment must be selected via the profile sele
During the instruction byte, write the address for the RAM,
0x0B. The serial port and RAM controller will work in
conjunction to determine the width of the profile and the ser
port will accept the defined number of 32-bit words
sequentially from the beginning address
Consider the following example:
The RAM Segment Control Word 1 lists the beginning
RAM address at 256 and the ending address at 511.
PS0 = 1 and PS1 = 0.
The instruction byte is 10001001.
The RAM controller would configur
256 32-
and sent to RAM Address 256. The next 32 bits would be pars
and sent to 257, and so forth, all the way through until the 256
word was sent (grand total of 8,192 data bits in this operatio
MODES OF OPERATION
Single-Tone Mode
In single-tone mode, the DDS core uses a single tuning word.
Whatever value is stored in FTW0 is supplied to the phase
accumulator. This value can only be changed manually, which is
done by writing a new value to FTW0 and by issuing an I/O
UPDATE. Phase adjustment is possible through the ph
offset registe
ontrol word for direct switch mode and a unique beginning
address value. In addition, the RAM enable bit is written true,
which enables the RAM, and the RAM destination bit is written
false, setting the RAM output to be the frequency tuning word.
The Profile<1:0> inputs are the 4-tone FSK data inputs. When
the profile is changed, the frequency tuning word stored in the
new profile is loaded into the phase accumulator and is used to
increment the currently stored value in a phase continuous
fashion. The phase offset word drives the phase-offset adder.
Two-tone FSK is accomplished by using only one profile pin f
data.
Programming the AD9953 for PSK modulation is similar to
FSK except the RAM destination bit is set to a Logic 1, enabling
the RAM output to drive the phase offset adder. The FTW0
drives the input to the phase accumulator. Toggling the profile
pins changes (modulates) the current phase value. The upper
14 bits of the RAM drive the phas
Bit <17:0> of the RAM output are unused when the RAM
ination bit is set. The no-dwell bit is a Don’t Care in d
sw ch mode.
Ra p-Up Mode
Ramp-up mode, in conjunction with the segmented RAM
capability, allows up to four different sweep profiles to be
programmed into the AD9953. The AD9953 is programmed for
ramp-up mode by writing the RAM enable bit true and
programming the RAM mode control bits of each profile to be
used to Logic 001(b). As in all m
the RAM destination
drives the phase accum
Upon starting a sweep (via an I/O UPDATE or change in
profile bits), the RAM address generator loads the RAM
segment beginning address bits of the current RSCW, driving
the RAM output from this address, and the ramp rate timer
loads the RAM segment address ramp rate bits. When the
ramp rate time
in
ra
c
a
c
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