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| 型号： | AD9953YSVZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/32页 |
| 文件大小： | 0K |
| 描述： | IC DDS DAC 14BIT 400MSPS 48-TQFP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 400MHz |
| 调节字宽（位）： | 32 b |
| 电源电压： | 1.71 V ~ 1.96 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TQFP 裸露焊盘 |
| 供应商设备封装： | 48-TQFP 裸露焊盘（7x7） |
| 包装： | 托盘 |
| 产品目录页面： | 552 (CN2011-ZH PDF) |
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AD9953
Rev. A | Page 17 of 32
ing mode).
igured as
ctive.
1. All non-IO digital functionality is suspended,
: Not Used
Down Bit
he clock input circuitry is enabled for
d the
External Power-Down Mode
ode,
high, the digital logic
red down. The DAC bias
the
CTL
ons are powered down. This includes
ake a significant amount of time to
YNC_CLK Disable Bit
static Logic 0
ate to keep noise generated by the digital circuitry at a
s
ming.
ntrol the various functions, features, and
og sections
ot Used
Bit
o use the auto-
e for SYNC_CLK inputs beyond 50 MHz,
ff.
nc function is enabled.
SYNC_IN pin will
cle. Unlike the software manual sync enable bit, this
is
red. See the
n for details.
,
T
y. The oscillator will respond to crystals in
ord controls the multiplier value out of the clock-
k. Valid values are decimal 4 to 20 (0x04 to
tside this range will bypass the clock
op (PLL) section for details.
nge of
100 MHz to 250 MHz. When CFR2<2> == 1, the VCO operates
in a range of 250 MHz to 400 MHz.
CFR1<9>: SDIO Input Only
CFR1<9> = 0 (default). The SDIO pin has bidirectional
operation (2-wire serial programm
CFR1<9> = 1. The serial data I/O pin (SDIO) is conf
an input only pin (3-wire serial programming mode).
CFR1<8>: LSB First
CFR1<8> = 0 (default). MSB first format is active.
CFR1<8> = 1. The serial interface accepts serial data in LSB
first format.
CFR1<7>: Digital Power-Down Bit
CFR1<7> = 0 (default). All digital functions and clocks are a
CFR1<7> =
lowering the power significantly.
CFR1<6>
CFR1<5>: DAC Power-Down Bit
CFR1<5> = 0 (default). The DAC is enabled for operation.
CFR1<5> = 1. The DAC is disabled and is in its lowest power
dissipation state.
CFR1<4>: Clock Input Power-
CFR1<4> = 0 (default). T
operation.
CFR1<4> = 1. The clock input circuitry is disabled an
device is in its lowest power dissipation state.
CFR1<3>:
CFR1<3> = 0 (default). The external power-down mode
selected is the rapid recovery power-down mode. In this m
when the PWRDWNCTL input pin is
and the DAC digital logic are powe
circuitry, PLL, oscillator, and clock input circuitry are not
powered down.
CFR1<3> = 1. The external power-down mode selected is
full power-down mode. In this mode, when the PWRDWN
ncti
input pin is high, all fu
the DAC and PLL, which t
power up.
CFR1<2>: Not Used
CFR1<1>: S
CFR1<1> = 0 (default). The SYNC_CLK pin is active.
e SYNC_CLK pin assumes a
CFR1<1> = 1. Th
st
minimum. However, the synchronization circuitry remain
active (internally) to maintain normal device ti
CFR1<0>: Not Used, Leave at 0
Control Function Register No. 2 (CFR2)
The CFR2 is used to co
modes of the AD9953, primarily related to the anal
of the chip.
CFR2<23:12>: N
CFR2<11>: High Speed Sync Enable
CFR2<11> = 0 (default). The high speed sync enhancement is off.
CFR2<11> = 1. The high speed sync enhancement is on. This
bit should be set when attempting t
synchronization featur
(200 MSPS SYSCLK). See the Syn
section for details.
CFR2<10>: Hardware Manual Sync Enable Bit
CFR2<10> = 0 (default). The hardware manual sync function is o
CFR2<10> = 1. The hardware manual sy
While this bit is set, a rising edge on the
cause the device to advance the SYNC_CLK rising edge by one
REFCLK cy
bit does not self clear. Once the hardware manual sync mode
enabled, it will stay enabled until this bit is clea
CFR2<9>: CRYSTAL OUT Enable Bit
CFR2<9> = 0 (default). The CRYSTAL OUT pin is inactive.
CFR2<9> = 1. The CRYSTAL OUT pin is active. When active
the crystal oscillator circuitry output drives the CRYSTAL OU
pin, which can be connected to other devices to produce a
reference frequenc
the range of 20 MHz to 30 MHz.
CFR2<8>: Not Used
CFR2<7:3>: Reference Clock Multiplier Control Bits
This 5-bit w
multiplier (PLL) bloc
0x14). Values entered ou
multiplier. See the Phase-Locked Lo
CFR2<2>: VCO Range Control Bit
This bit is used to control the range setting on the VCO.
When CFR2<2> == 0 (default), the VCO operates in a ra
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| AD9953YSVZ-REEL7 | 功能描述:IC DDS DAC 14BIT 1.8V 48TQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| AD9954 | 制造商:AD 制造商全称:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9954/PCB | 制造商:Analog Devices 功能描述:AD9954 400 MSPS DDS W/ 14 BIT DAC EVALBD - Bulk 制造商:Analog Devices 功能描述:EVALUATION KIT ((NS)) |
| AD9954/PCBZ | 功能描述:BOARD EVAL FOR 9954 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:AgileRF™ 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9954/PCBZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
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