- 您现在的位置：买卖IC网 > PDF目录16425 > AD9983A/PCBZ (Analog Devices Inc)KIT EVALUATION AD9983A PDF资料下载
参数资料
| 型号： | AD9983A/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/44页 |
| 文件大小： | 0K |
| 描述： | KIT EVALUATION AD9983A |
| 标准包装： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 视频，视频处理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9983A |
| 主要属性： | 3 x 8-Bit 140 MSPS ADC's |
| 次要属性： | 集成式 PLL 和 VCO |
| 已供物品： | 板 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页
AD9983A
Rev. 0 | Page 20 of 44
COAST TIMING
In most computer systems, the Hsync signal is provided
continuously on a dedicated wire. In these systems, the coast
input and function are unnecessary and should not be used.
In some systems, however, Hsync is disturbed during the
vertical sync period (Vsync). In some cases, Hsync pulses
disappear. In other systems, such as those that employ
composite sync (Csync) signals or embedded sync-on-green,
Hsync may include equalization pulses or other distortions
during Vsync. To avoid upsetting the clock generator during
Vsync, it is important to ignore these distortions. If the pixel
clock PLL sees extraneous pulses, it attempts to lock to this new
frequency, and will have changed frequency by the end of the
Vsync period. It then takes a few lines of correct Hsync timing
to recover at the beginning of a new frame, resulting in a tearing
of the image at the top of the display.
The COAST input is provided to eliminate this problem. It is an
asynchronous input that disables the PLL input and holds the
clock at its current frequency. The PLL can free run for several
lines without significant frequency drift. Coast can be generated
internally by the AD9983A (see Register 0x18) or can be
provided externally by the graphics controller.
When internal coast is selected (Register 0x18, Bit 7 = 0, and
Register 0x14, Bits[7:6] to select source), Vsync is used as a
basis for determining the position of COAST. The internal coast
signal is enabled a programmed number of Hsync periods
before the periodic Vsync signal (Precoast Register 0x16) and
dropped a programmed number of Hsync periods after Vsync
(Postcoast Register 0x17). It is recommended that the Vsync
filter be enabled when using the internal coast function to allow
the AD9983A to determine precisely the number of Hsyncs/Vsync
and their location. In many applications where disruptions
occur and coast is used, values of 2 for Precoast and 10d for
Postcoast are sufficient to avoid most extraneous pulses.
OUTPUT FORMATTER
The output formatter is capable of generating several output
formats to be presented to the 24 data output pins. The output
formats and the pin assignments for each format are listed in
Table 12. Also, there are several clock options for the output
clock. The user may select the pixel clock, a 90° phase-shifted
pixel clock, a 2× pixel clock, or a fixed frequency 40 MHz clock
for test purposes. The output clock may also be inverted.
Data output is available as 24-pin RGB or YCbCr, or if either
4:2:2 or 4:4:4 DDR is selected, a secondary channel is available.
This secondary channel is always 4:2:2 DDR and allows the
flexibility of having a second channel with the same video data
that can be utilized by either another display or even a storage
device. Depending on the choice of output modes, the primary
output can be 24 pins, 16 pins, or as little as 12 pins.
Mode Descriptions
4:4:4
All channels come out with their 8 data bits at the same time.
Data is aligned to the negative edge of the clock for easy capture.
This is the normal 24-bit output mode for RGB or 4:4:4 YCbCr.
4:2:2
Red and green channels contain 4:2:2 formatted data (16 pins)
with Y data on the green channel and Cb, Cr data on the red
channel. Data is aligned to the negative edge of the clock. The
blue channel contains the secondary channel with Cb, Y, Cr, Y
formatted 4:2:2 DDR data. The data edges are aligned to both
edges of the pixel clock, so use of the 90° clock may be necessary to
capture the DDR data.
4:4:4 DDR
This mode puts out full 4:4:4 data on 12 bits of the red and
green channels, thus saving 12 pins. The first half (RGB[11:0])
of the 24-bit data is sent on the rising edge and the second half
(RGB[23:12]) is sent on the falling edge. DDR 4:2:2 data is sent
on the blue channel, as in 4:2:2 mode.
RGB [23:0] = R [7:0] + G [7:0] + B [7:0], so
RGB [23:12] = R [7:0] + G [7:4] and
RGB [11:0] = G [3:0] + B [7:0]
Table 12. Output Formats
Port
Red
Green
Blue
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
4:4:4
Red/Cr
Green/Y
Blue/Cb
Cb, Cr
Y
DDR 4:2:2
↑ Cb, Cr ↓ Y, Y
4:4:4 DDR
DDR
↑2 G [3:0]
DDR
↑ B [7:4]
DDR
↑ B [3:0]
N/A
DDR 4:2:2
↑ Cb, Cr
DDR
↓2 R [7:0]
DDR
↓ G [7:4]
N/A
DDR 4:2:2
↓ Y, Y
1 For 4:2:2 Cb sent before Cr.
2 Arrows in table indicate clock edge. Rising edge of clock =
↑, falling edge = ↓.
相关PDF资料 |
PDF描述 |
|---|---|
| VI-J43-EX | CONVERTER MOD DC/DC 24V 75W |
| GBC15DREN-S93 | CONN EDGECARD 30POS .100 EYELET |
| S01-01-R | SOLDER SLEEVE IMMERS RESIS .650" |
| UPA1A102MPD6TD | CAP ALUM 1000UF 10V 20% RADIAL |
| H3AAH-6436G | IDC CABLE - HSC64H/AE64G/HSC64H |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9983KSTZ-110 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9983KSTZ-140 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9983KSTZ-170 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9984A | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance 10-Bit Display Interface |
| AD9984A/PCB | 制造商:Analog Devices 功能描述:DISPLAY INTRFC - Bulk |
发布紧急采购，3分钟左右您将得到回复。