参数资料
型号: ADAU1381BCPZ-RL
厂商: Analog Devices Inc
文件页数: 46/84页
文件大小: 0K
描述: IC AUDIO CODEC STEREO LN 32LFCSP
标准包装: 5,000
类型: 立体声音频
数据接口: 串行,SPI?
分辨率(位): 24 b
ADC / DAC 数量: 2 / 2
三角积分调变:
S/N 比,标准 ADC / DAC (db): 97 / 100
动态范围,标准 ADC / DAC (db): 96.5 / 100
电压 - 电源,模拟: 1.8 V ~ 3.65 V
电压 - 电源,数字: 1.63 V ~ 3.65 V
工作温度: -25°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘,CSP
供应商设备封装: 32-LFCSP-VQ
包装: 带卷 (TR)
配用: EVAL-ADAU1381Z-ND - BOARD EVALUATION FOR ADAU1381
ADAU1381
Rev. B | Page 50 of 84
Register 16398 (0x400E), Record Gain Left PGA
The record gain left PGA control register controls the left channel
input PGA. This register configures the input for either differ-
ential or single-ended signals and sets the left channel input
recording volume.
Bits[7:5], Left Input Gain
These bits set the left channel analog microphone input PGA gain.
Bit 2, Single-Ended Left Input Enable
If this bit is high (enabled), a single-ended input can be input on
the LMIC pin and gained by the PGA. The positive differential
input pin (LMICP) is disabled, and the complementary input of
the PGA is switched to common mode.
Bit 1, Record Path Left Mute
This bit mutes the left channel input PGA.
Bit 0, Left PGA Enable
This bit enables the left channel input PGA
Table 37. Record Gain Left PGA Register
Bits
Description
Default
[7:5]
Left input gain
000
000: 0 dB
001: 6 dB
010: 10 dB
011: 14 dB
100: 17 dB
101: 20 dB
110: 26 dB
111: 32 dB
[4:3]
Reserved
2
Single-ended left input enable
0
0: disabled
1: enabled
1
Record path left mute
0
0: muted
1: unmuted
0
Left PGA enable
0
0: disabled
1: enabled
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