参数资料
型号: ADAU1381BCPZ-RL
厂商: Analog Devices Inc
文件页数: 64/84页
文件大小: 0K
描述: IC AUDIO CODEC STEREO LN 32LFCSP
标准包装: 5,000
类型: 立体声音频
数据接口: 串行,SPI?
分辨率(位): 24 b
ADC / DAC 数量: 2 / 2
三角积分调变:
S/N 比,标准 ADC / DAC (db): 97 / 100
动态范围,标准 ADC / DAC (db): 96.5 / 100
电压 - 电源,模拟: 1.8 V ~ 3.65 V
电压 - 电源,数字: 1.63 V ~ 3.65 V
工作温度: -25°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘,CSP
供应商设备封装: 32-LFCSP-VQ
包装: 带卷 (TR)
配用: EVAL-ADAU1381Z-ND - BOARD EVALUATION FOR ADAU1381
ADAU1381
Rev. B | Page 67 of 84
Register 16425 (0x4029), Playback Power Management
This register controls the unity current supplied to each functional
block described. Within the functional blocks, the current can
be multiplied. Normal operation has a base current of 2.5 μA,
enhanced performance has a base current of 3 μA, power saving
has a base current of 2 μA, and extreme power saving has a base
current of 1.5 μA. Enhanced performance mode offers the best
audio quality but also uses the most current.
Bit [7:6], Speaker Amplifier Bias Control
These bits control the amount of unity bias current allotted to
the speaker amplifier.
Bits[5:4], DAC Bias Control
These bits control the amount of unity bias current allotted to
the DAC.
Bits[3:2], Back-End Bias Control
These bits control the amount of unity bias current allotted to
the playback mixers and amplifiers.
Bit 1, Back-End Right Enable
This bit enables the playback mixers and amplifiers.
Bit 0, Back-End Left Enable
This bit enables the playback mixers and amplifiers.
Table 55. Playback Power Management Register
Bits
Description
Default
[7:6]
Speaker amplifier bias control
00
00: normal operation
01: power saving
10: enhanced performance
00: reserved
[5:4]
DAC bias control
00
00: normal operation
01: extreme power saving
10: power saving
00: enhanced performance
[3:2]
Back-end bias control
00
00: normal operation
01: extreme power saving
10: power saving
00: enhanced performance
1
Back-end right enable
0
0: disabled
1: enabled
0
Back-end left enable
0
0: disabled
1: enabled
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