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参数资料
| 型号： | ADC081500CIYB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter |
| 中文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP128 |
| 封装： | MS-026BFB, LQFP-128 |
| 文件页数： | 11/28页 |
| 文件大小： | 830K |
| 代理商： | ADC081500CIYB |
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Converter Electrical Characteristics
(Continued)
The following specifications apply after calibration for V
= V
= +1.9V
, OutV = 1.9V, V
(a.c. coupled) Full Scale Range =
differential 870mV
, C
= 10 pF, Differential (a.c. coupled) sinewave input clock, f
CLK
= 1.5 GHz at 0.5V
with 50% duty
cycle, V
= Floating, Normal Control Mode, Single Data Rate Mode, R
= 3300
0.1%, Analog Signal Source Impedance
= 100
Differential.
Boldface limits apply for T
A
= T
MIN
to T
MAX
. All other limits T
A
= 25C, unless otherwise noted. (Notes 6,
7)
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
AC ELECTRICAL CHARACTERISTICS
Calibration delay determined by
pin 127
Calibration delay determined by
pin 127
t
CalDly
See Section 1.1.1,
Figure 9
,
(Note 11)
See Section 1.1.1,
Figure 9
,
(Note 11)
2
25
Clock Cycles
(min)
Clock Cycles
(max)
t
CalDly
2
31
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum
Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
Note 2:
All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
Note 3:
When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than V
), the current at that pin should be limited to
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
This limit is not placed upon the power, ground and digital output pins.
Note 4:
Human body model is 100 pF capacitor discharged through a 1.5 k
resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 5:
See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”.
Note 6:
The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
20153104
Note 7:
To guarantee accuracy, it is required that V
and V
be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally,
achieving rated performance requires that the backside exposed pad be well grounded.
Note 8:
Typical figures are at T
A
= 25C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
Level).
Note 9:
Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,
therefore, is a combination of Full-Scale Error and Reference Voltage Error. See
Figure 2
. For relationship between Gain Error and Full-Scale Error, see Specification
Definitions for Gain Error.
Note 10:
The analog and clock input capacitances are die capacitances only.Additional package capacitances of 0.65 pF differential and 0.95 pF each pin to ground
are isolated from the die capacitances by lead and bond wire inductances.
Note 11:
This parameter is guaranteed by design and is not tested in production.
Note 12:
This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 13:
The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die
capacitances by lead and bond wire inductances.
Note 14:
The ADC081500 converter has two LVDS output buses, which each clock data out at one half the sample rate. The second bus (D0 through D7) has a
pipeline latency that is one Input Clock cycle less than the latency of the first bus (Dd0 through Dd7).
Note 15:
Tying V
BG
to the supply rail will increase the output offset voltage (V
OS
) by 400mv (typical), as shown in the V
OS
specification above. Tying V
BG
to the
supply rail will also affect the differential LVDS output voltage (V
OD
), causing it to increase by 40mV (typical).
A
www.national.com
11
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相关代理商/技术参数 |
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|---|---|
| ADC081500CIYB/NOPB | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ADC081500DEV | 制造商:NSC 制造商全称:National Semiconductor 功能描述:High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter |
| ADC081500EVAL | 制造商:NSC 制造商全称:National Semiconductor 功能描述:High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter |
| ADC0816 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit レP Compatible A/D Converters with 16-Channel Multiplexer |
| ADC0816_07 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit レP Compatible A/D Converters with 16-Channel Multiplexer |
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