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参数资料
| 型号： | ADC081500CIYB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter |
| 中文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP128 |
| 封装： | MS-026BFB, LQFP-128 |
| 文件页数： | 18/28页 |
| 文件大小： | 830K |
| 代理商： | ADC081500CIYB |
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1.0 Functional Description
(Continued)
controls are disabled. These pins are OutV (pin 3), OutEdge/
DDR (pin 4), FSR (pin 14) and CalDly (pin 127). See Section
1.2 for details on the Extended Control mode.
1.1.4 The Analog Inputs
The ADC081500 must be driven with a differential input
signal. Operation with a single-ended signal is not recom-
mended. It is important that the input signals are either a.c.
coupled to the inputs with the V
pin grounded, or d.c.
coupled with the V
pin left floating. An input common
mode voltage equal to the V
CMO
output must be provided
when d.c. coupling is used.
Two full-scale range settings are provided with pin 14 (FSR).
A high on pin 14 causes an input full-scale range setting of
870 mV
, while grounding pin 14 causes an input full-scale
range setting of 650 mV
P-P
.
In the Extended Control mode, the full-scale input range can
be set to values between 560 mV
P-P
and 840 mV
P-P
through
a serial interface. See Section 2.2
1.1.5 Clocking
The ADC081500 must be driven with an a.c. coupled, differ-
ential clock signal. Section 2.3 describes the use of the clock
input pins. A differential LVDS output clock is available for
use in latching the ADC output data into whatever device is
used to receive the data. The ADC081500 offers options for
output clocking. These options include a choice of which
DCLK (DCLK) edge the output data transitions on, and a
choice of Single Data Rate (SDR) or Double Data Rate
(DDR) outputs.
The ADC081500 also has the option to use a duty cycle
corrected clock receiver as part of the input clock circuit. This
feature is enabled by default and provides improved ADC
clocking. This circuitry allows the ADC to be clocked with a
signal source having a duty cycle ratio of 80 / 20 % (worst
case).
1.1.5.1 OutEdge Setting
To help ease data capture in the SDR mode, the output data
may be caused to transition on either the positive or the
negative edge of the output data clock (DCLK). This is
chosen with the OutEdge input (pin 4). A high on the Out-
Edge input pin causes the output data to transition on the
rising edge of DCLK, while grounding this input causes the
output to transition on the falling edge of DCLK. See Section
2.4.3.
1.1.5.2 Double Data Rate
Achoice of single data rate (SDR) or double data rate (DDR)
output is offered. With single data rate the output clock
(DCLK) frequency is the same as the data rate of the two
output buses. With double data rate the DCLK frequency is
half the data rate and data is sent to the outputs on both
edges of DCLK. DDR clocking is enabled in Normal Control
mode by allowing pin 4 to float.
1.1.6 The LVDS Outputs
The data outputs, the Out Of Range (OR) and DCLK, are
LVDS. Output current sources provide 3 mAof output current
to a differential 100 Ohm load when the OutV input (pin 14)
is high or 2.2 mA when the OutV input is low. For short LVDS
lines and low noise systems, satisfactory performance may
be realized with the OutV input low, which results in lower
power consumption. If the LVDS lines are long and/or the
system in which the ADC081500 is used is noisy, it may be
necessary to tie the OutV pin high.
The LVDS data output have a typical common mode voltage
of 800mV when the V
pin is unconnected and floating.
This common mode voltage can be increased to 1.2V by
tying the V
BG
pin to V
A
if a higher common mode is required.
1.1.7 Power Down
The ADC081500 is in the active state when the Power Down
pin (PD) is low. When the PD pin is high, the device is in the
power down mode. In this power down mode the data output
pins (positive and negative) are put into a high impedance
state and the devices power consumption is reduced to a
minimal level. The DCLK+/- and OR +/- are not tri-stated,
they are weakly pulled down to ground internally. Therefore
when the device is powered down the DCLK +/- and OR +/-
should not be terminated to a DC voltage. Also note, that
upon return to normal operation after power down mode, the
pipeline will contain meaningless information.
If the PD input is brought high while a calibration is running,
the device will not go into power down until the calibration
sequence is complete. However, if power is applied and PD
is already high, the device will not begin the calibration
sequence until the PD input goes low. If a manual calibration
is requested while the device is powered down, the calibra-
tion will not begin at all. That is, the manual calibration input
is completely ignored in the power down state.
1.2 NORMAL/EXTENDED CONTROL MODES
The ADC081500 may be operated in one of two modes. In
the simpler Normal Control mode, the user affects available
configuration and control of the device through several con-
trol pins. The Extended Control mode provides additional
configuration and control options through a serial interface
and a set of 3 registers. The two control modes are selected
with pin 14 (FSR/ECE: Extended Control Enable). The
choice of control modes is required to be a fixed selection
and is not intended to be switched dynamically while the
device is operational.
Table 1
shows how several of the device features are af-
fected by the control mode chosen.
A
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADC081500CIYB/NOPB | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ADC081500DEV | 制造商:NSC 制造商全称:National Semiconductor 功能描述:High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter |
| ADC081500EVAL | 制造商:NSC 制造商全称:National Semiconductor 功能描述:High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter |
| ADC0816 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit レP Compatible A/D Converters with 16-Channel Multiplexer |
| ADC0816_07 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit レP Compatible A/D Converters with 16-Channel Multiplexer |
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