参数资料
型号: ADC1113D125HN
厂商: NXP Semiconductors N.V.
元件分类: 外设及接口
英文描述: Dual 11 bits ADC; 125 Msps; serial JESD204A
封装: ADC1113D125HN/C1<SOT684-7 (HVQFN56)|<<http://www.nxp.com/packages/SOT684-7.html<1<Always Pb-free,;ADC1113D125HN/C1<SOT684-7 (HVQFN56)|<<http://www.nxp.com/packages/SOT684
文件页数: 2/41页
文件大小: 536K
代理商: ADC1113D125HN
ADC1113D125
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NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 10 February 2011
10 of 41
NXP Semiconductors
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
10.2 Clock and digital output timing
[1]
Typical values measured at VDDA =3V, VDDD = 1.8 V, Tamb =25 °C. Minimum and maximum values are across the full temperature
range Tamb = 40 °C to +85 °C at VDDA =3 V, VDDD = 1.8 V; VI (INAP, INBP) VI (INAM, INBM) = 1 dBFS; internal reference mode;
100 W differential applied to serial outputs; unless otherwise specified.
10.3 Serial output timing
The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions
are:
3.125 Gbps data rate
Tamb =25°C
DC coupling with two different receiver common-mode voltages
Table 7.
Characteristics[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Clock timing input: pins CLKP and CLKM
fclk
clock frequency
100
-
125
Msps
tlat(data)
data latency time
-
14
-
clock cycle
δ
clk
clock duty cycle
DCS_EN = logic 1
30
50
70
%
DCS_EN = logic 0
45
50
55
%
td(s)
sampling delay time
-
0.8
-
ns
twake
wake-up time
-
76
-
μs
Fig 3.
Eye diagram at 1 V receiver common-mode
005aaa088
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