参数资料
型号: ADC1113D125HN
厂商: NXP Semiconductors N.V.
元件分类: 外设及接口
英文描述: Dual 11 bits ADC; 125 Msps; serial JESD204A
封装: ADC1113D125HN/C1<SOT684-7 (HVQFN56)|<<http://www.nxp.com/packages/SOT684-7.html<1<Always Pb-free,;ADC1113D125HN/C1<SOT684-7 (HVQFN56)|<<http://www.nxp.com/packages/SOT684
文件页数: 22/41页
文件大小: 536K
代理商: ADC1113D125HN
ADC1113D125
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 10 February 2011
29 of 41
NXP Semiconductors
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
[1]
F: Octets per frame clock cycle
HD: High-density mode
K: Frame per multi-frame
M: Converters per device
L: Lane per converter device
CS: Number of control bits per conversion sample
CF: Control words per frame clock cycle and link
S: Number of samples transmitted per single converter per frame cycle
Table 28.
Ser_Cfg_Setup (address 0803h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 4 -
-
0000
not used
3 to 0 CFG_SETUP[3:0]
R/W
1000
quick configuration of JESD204A. These settings overrule the
configuration of pins CFG3 to CFG0 (see Table 29).
Table 29.
JESD204A configuration table
CFG_SETUP[3:0] ADC A ADC B
Lane 0
Lane 1
Comment
00000
ON
20
9
2
(F
× K) ≥ 17
1
0
1
10001
ON
OFF
3
0
6
2
1
(F
× K) ≥ 17
1
0
1
20010
ON
OFF
ON
30
6
2
1
(F
× K) ≥ 17
1
0
1
30011
ON
OFF
ON
11
17
1
2
(F
× K) ≥ 17
1
0
1
40100
OFF
ON
11
17
1
2
(F
× K) ≥ 17
1
0
1
50101
ON
OFF
ON
OFF
2
0
9
1
(F
× K) ≥ 17
1
0
1
60110
ON
OFF
ON
20
9
1
(F
× K) ≥ 17
1
0
1
70111
OFF
ON
OFF
2
0
9
1
(F
× K) ≥ 17
1
0
1
81000
OFF
ON
OFF
ON
20
9
1
(F
× K) ≥ 17
1
0
1
9
1001
reserved
10
1010
reserved
11
1011
reserved
12
1100
reserved
13
1101
reserved
14
1110
ON
2
0
9
2
test: loop
alignment
10
1
15
1111
OFF
2
0
9
2
chip
power-down
10
1
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