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| 型号： | ADE5569ASTZF62-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 116/156页 |
| 文件大小： | 0K |
| 描述： | IC METER/8052/RTC/LCD DRV 64LQFP |
| 标准包装： | 1,500 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 带卷 (TR) |
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ADE5166/ADE5169/ADE5566/ADE5569
Table 114. Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, Address 0x88)
Data Sheet
Bit
7
Bit Address
0x8F
Mnemonic
TF1
Default
0
Description
Timer 1 overflow flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware
when the program counter (PC) vectors to the interrupt service routine.
6
0x8E
TR1
0
Timer 1 run control bit. Set by the user to turn on Timer/Counter 1. Cleared by the user to turn
off Timer/Counter 1.
5
0x8D
TF0
0
Timer 0 overflow flag. Set by hardware on a Timer/Counter 0 overflow. Cleared by hardware
when the PC vectors to the interrupt service routine.
4
0x8C
TR0
0
Timer 0 run control bit. Set by the user to turn on Timer/Counter 0. Cleared by the user to turn
off Timer/Counter 0.
3
0x8B
IE1 1
0
External Interrupt 1 (INT1) flag. Set by hardware by a falling edge or by a zero level applied to
the external interrupt pin, INT1, depending on the state of Bit IT1. Cleared by hardware when
the PC vectors to the interrupt service routine only if the interrupt was transition activated. If level
activated, the external requesting source, rather than the on-chip hardware, controls the
request flag.
2
0x8A
IT1 1
0
External Interrupt 1 (IE1) trigger type. Set by software to specify edge sensitive detection, that is,
a 1-to-0 transition. Cleared by software to specify level sensitive detection, that is, zero level.
1
0x89
IE0 1
0
External Interrupt 0 (INT0) flag. Set by hardware by a falling edge or by a zero level applied to
the external interrupt pin, INT0, depending on the state of Bit IT0. Cleared by hardware when
the PC vectors to the interrupt service routine only if the interrupt was transition activated. If
level activated, the external requesting source, rather than the on-chip hardware, controls the
request flag.
0
0x88
IT0 1
0
External Interrupt 0 (IE0) trigger type. Set by software to specify edge sensitive detection, that is,
a 1-to-0 transition. Cleared by software to specify level sensitive detection, that is, zero level.
1
These bits are not used to control Timer/Counter 0 and Timer/Counter 1 but are, instead, used to control and monitor the external INT0 and INT1 interrupt pins.
Table 115. Timer/Counter 2 Control SFR (T2CON, Address 0xC8)
Bit
7
Bit Address
0xCF
Mnemonic
TF2
Default
0
Description
Timer 2 overflow flag. Set by hardware on a Timer 2 overflow. TF2 cannot be set when either
RCLK = 1 or TCLK = 1. Cleared by user software.
6
0xCE
EXF2
0
Timer 2 external flag. Set by hardware when either a capture or reload is caused by a negative
transition on the T2EX pin and EXEN2 = 1. Cleared by user software.
5
0xCD
RCLK
0
Receive clock enable bit. Set by the user to enable the serial port to use Timer 2 overflow pulses
for its receive clock in Serial Port Mode 1 and Serial Port Mode 3. Cleared by the user to enable
Timer 1 overflow to be used for the receive clock.
4
0xCC
TCLK
0
Transmit clock enable bit. Set by the user to enable the serial port to use Timer 2 overflow pulses
for its transmit clock in Serial Port Mode 1 and Serial Port Mode 3. Cleared by the user to enable
Timer 1 overflow to be used for the transmit clock.
3
0xCB
EXEN2
0
Timer 2 external enable flag. Set by the user to enable a capture or reload to occur as a result of
a negative transition on the T2EX pin if Timer 2 is not being used to clock the serial port. Cleared
by the user for Timer 2 to ignore events at T2EX.
2
1
0xCA
0xC9
TR2
C/T2
0
0
Timer 2 start/stop control bit. Set by the user to start Timer 2. Cleared by the user to stop Timer 2.
Timer 2 timer or counter function select bit. Set by the user to select the counter function (input
from the external T2 pin). Cleared by the user to select the timer function (input from the on-chip core
clock).
0
0xC8
CAP2
0
Timer 2 capture/reload select bit. Set by the user to enable captures on negative transitions at
the T2EX pin if EXEN2 = 1. Cleared by the user to enable autoreloads with Timer 2 overflows or
negative transitions at the T2EX pin when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is
ignored and the timer is forced to autoreload on Timer 2 overflow.
Rev. D | Page 116 of 156
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