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参数资料
| 型号： | ADE7518ASTZF8-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 36/128页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER MCU 8K 64LQFP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 1,500 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 带卷 (TR) |
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ADE7518
Address
Length
Signed/
MADDPT[6:0]
0x29
0x2A
Mnemonic
CF2NUM
CF2DEN
R/W
R/W
R/W
(Bits)
16
16
Unsigned
U
U
Default
0
0x003F
Description
Sets CF2 numerator register.
Sets CF2 denominator register.
0x3B
0x3C
0x3D
0x3E
0x3F
Reserved
Reserved
Reserved
Reserved
Reserved
0
0x0300
0
0
0
This register must be kept at its default value for proper operation.
This register must be kept at its default value for proper operation.
This register must be kept at its default value for proper operation.
This register must be kept at its default value for proper operation.
This register must be kept at its default value for proper operation.
ENERGY MEASUREMENT INTERNAL REGISTERS DETAILS
Table 31. MODE1 Register (0x0B)
Bit
7
6
5
4
3
2
1
0
Mnemonic
SWRST
DISZXLPF
Reserved
SWAPBITS
PWRDN
DISCF2
DISCF1
DISHPF
Default
0
0
0
0
0
1
1
0
Description
Setting this bit resets all of the energy measurement registers to their default values.
Setting this bit disables the zero-crossing low-pass filter.
This bit must be kept at its default value for proper operation.
Setting this bit swaps CH1 ADC and CH2 ADC.
Setting this bit powers down voltage and current ADCs.
Setting this bit disables Frequency Output CF2.
Setting this bit disables Frequency Output CF1.
Setting this bit disables the HPFs in voltage and current channels.
Table 32. MODE2 Register (0x0C)
Bit
7 to 6
Mnemonic
CF2SEL[1:0]
Default
01
Description
Configuration Bits for CF2 Output.
CF2SEL[1:0] Result
00
01
1x
CF2 frequency is proportional to active power.
CF2 frequency is proportional to reactive power.
CF2 frequency is proportional to apparent power or I rms .
5 to 4
CF1SEL[1:0]
00
Configuration Bits for CF1 Output.
CF1SEL[1:0] Result
00
01
1x
CF1 frequency is proportional to active power.
CF1 frequency is proportional to reactive power.
CF1 frequency is proportional to apparent power or I rms .
3
VARMSCFCON
0
Configuration Bits for Apparent Power or I rms for CF1, CF2 Outputs, and VA Accumulation
Registers (VAHR, RVAHR, and LVAHR). Note that CF1 cannot be proportional to VA if CF2 is
proportional to I rms and vice versa.
VARMSCFCON Result
0
1
If CF1SEL[1:0] = 1x, CF1 is proportional to VA.
If CF2SEL[1:0] = 1x, CF2 is proportional to VA.
If CF1SEL[1:0] = 1x, CF1 is proportional to I rms .
If CF2SEL[1:0] = 1x, CF2 is proportional to I rms .
2
1
ZXRMS
FREQSEL
0
Logic 1 enables update of rms values synchronously to Voltage ZX.
Configuration Bits to Select Period or Frequency Measurement for PER_FREQ Register (0x0A).
FREQSEL Result
0
1
PER_FREQ register holds a period measurement.
PER_FREQ register holds a frequency measurement.
0
WAVEN
0
When this bit is set, the waveform sampling mode is enabled.
Rev. 0 | Page 36 of 128
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