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参数资料
| 型号： | ADE7518ASTZF8-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 61/128页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER MCU 8K 64LQFP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 1,500 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 带卷 (TR) |
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ADE7518
ENERGY-TO-FREQUENCY CONVERSION
The ADE7518 also provides two energy-to-frequency conversions
for calibration purposes. After initial calibration at manufacturing,
the manufacturer or end customer often verifies the energy
meter calibration. One convenient way to do this is for the
manufacturer to provide an output frequency that is propor-
tional to the active power, reactive power, apparent power,
or I rms under steady load conditions. This output frequency
can provide a simple, single-wire, optically isolated interface to
external calibration equipment. Figure 65 illustrates the energy-
to-frequency conversion in the ADE7518.
MODE 2 REGISTER 0x0C
VARMSCFCON CFxSEL[1:0]
Pulse Output Configuration
The two pulse output circuits have separate configuration bits
in the MODE2 register (0x0C). Setting the CFxSEL bits to
0b00, 0b01, or 0b1x configures the DFC to create a pulse output
proportional to active power, to reactive power, or to apparent
power or I rms , respectively.
The selection between I rms and apparent power is done by the
VARMSCFCON bit in the MODE2 register (0x0C). With this
selection, CF2 cannot be proportional to apparent power if CF1
is proportional to I rms , and CF1 cannot be proportional to apparent
power if CF2 is proportional to I rms .
Pulse Output Characteristic
The pulse output for both DFCs stays low for 90 ms if the pulse
I rms
CFxNUM
period is longer than 180 ms (5.56 Hz). If the pulse period is
shorter than 180 ms, the duty cycle of the pulse output is 50%.
VA
VAR
DFC
÷
CFx PULSE
OUTPUT
The pulse output is active low and should preferably be connected
to an LED, as shown in Figure 66.
V DD
WATT
CFxDEN
CF
Figure 65. Energy-to-Frequency Conversion
Two digital-to-frequency converters (DFC) are used to generate
the pulsed outputs. When WDIV = 0 or 1, the DFC generates a
pulse each time 1 LSB in the energy register is accumulated. An
output pulse is generated when a CFxNUM/CFxDEN number
of pulses are generated at the DFC output. Under steady load
conditions, the output frequency is proportional to the active
power, reactive power, apparent power, or I rms , depending on
the CFxSEL bits in the MODE2 register (0x0C).
Both pulse outputs can be enabled or disabled by clearing or
setting Bit DISCF1 and Bit DISCF2 in the MODE1 register
(0x0B), respectively.
Both pulse outputs set separate flags in the Interrupt Status 2 SFR
(MIRQSTM, 0xDD), CF1 and CF2. If the CF1 and CF2 enable
bits in the Interrupt Enable 2 SFR (MIRQENM, 0xDA) are set,
the 8052 core has a pending ADE interrupt. The ADE interrupt
stays active until the CF1 or CF2 status bits are cleared (see the
Energy Measurement Interrupts section).
Figure 66. CF Pulse Output
The maximum output frequency with ac input signals at
full scale and CFxNUM = 0x00 and CFxDEN = 0x00 is
approximately 21.1 kHz.
The ADE7518 incorporates two registers per DFC, CFxNUM[15:0]
and CFxDEN[15:0], to set the CFx frequency. These are unsigned
16-bit registers that can be used to adjust the CFx frequency to
a wide range of values. These frequency scaling registers are
16-bit registers that can scale the output frequency by 1/2 16 to 1
with a step of 1/2 16 .
If 0 is written to any of these registers, 1 is applied to the regis-
ter. The ratio CFxNUM/CFxDEN should be less than 1 to
ensure proper operation. If the ratio of the CFxNUM/CFxDEN
registers is greater than 1, the register values are adjusted to a
ratio of 1. For example, if the output frequency is 1.562 kHz and
the content of CFxDEN is 0 (0x000), the output frequency can
be set to 6.1 Hz by writing 0xFF to the CFxDEN register.
Rev. 0 | Page 61 of 128
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