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参数资料
| 型号： | ADE7518ASTZF8-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 38/128页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER MCU 8K 64LQFP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 1,500 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 带卷 (TR) |
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ADE7518
Table 35. ACCMODE Register (0x0F)
Bit
7 to 6
5
Mnemonic
Reserved
VARSIGN
Default
0
0
Description
These bits should be left at their default value for proper operation.
Configuration bit to select the event that triggers a reactive power sign interrupt. If set to 0, VARSIGN
interrupt occurs when reactive power changes from positive to negative. If this bit is set to 1, VARSIGN
interrupt occurs when reactive power changes from negative to positive.
4
APSIGN
0
Configuration bit to select event that triggers an active power sign interrupt. If set to 0, APSIGN
interrupt occurs when active power changes from positive to negative. If this bit is set to 1, APSIGN
interrupt occurs when active power changes from negative to positive.
3
2
ABSVARM
SAVARM
0
0
Logic 1 enables absolute value accumulation of reactive power in energy register and pulse output.
Logic 1 enables reactive power accumulation depending on the sign of the active power. If active
power is positive, VAR is accumulated as it is. If active power is negative, the sign of the VAR is
reversed for the accumulation. This accumulation mode affects both the VAR registers (VARHR,
RVARHR, LVARHR) and the pulse output when connected to VAR.
1
POAM
0
Logic 1 enables positive-only accumulation of active power in the WATTHR energy register and
pulse output.
0
ABSAM
0
Logic 1 enables absolute value accumulation of active power in the WATTHR energy register and
pulse output.
Table 36. GAIN Register (0x1B)
Bit
7 to 5
Mnemonic
PGA2[2:0]
Default
000
Description
These bits define the voltage channel input gain.
PGA2[2:0] Result
000
001
010
011
100
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
4
3
Reserved
CFSIGN_OPT
0
0
Reserved.
This bit defines where the CF change of sign detection (APSIGN or VARSIGN) is implemented.
CFSIGN_OPT Result
0
1
Filtered power signal
On a per CF pulse basis
2 to 0
PGA1[2:0]
000
These bits define the current channel input gain.
PGA1[2:0] Result
000
001
010
011
100
INTERRUPT STATUS/ENABLE SFRS
Table 37. Interrupt Status 1 SFR (MIRQSTL, 0xDC)
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Bit
7
6
5
4
3
2
1
0
Interrupt Flag
ADEIRQFLAG
Reserved
Reserved
VARSIGN
APSIGN
VANOLOAD
RNOLOAD
APNOLOAD
Description
This bit is set if any of the ADE status flags that are enabled to generate an ADE interrupt are set. This bit is
automatically cleared when all of the enabled ADE status flags are cleared.
Reserved.
Reserved.
Logic 1 indicates that the reactive power sign has changed according to the configuration of the ACCMODE register.
Logic 1 indicates that the active power sign has changed according to the configuration of the ACCMODE register.
Logic 1 indicates that an interrupt has been caused by an apparent power no load detection. This interrupt is
also used to reflect the part entering the I rms no load mode.
Logic 1 indicates that an interrupt has been caused by a reactive power no load detection.
Logic 1 indicates that an interrupt has been caused by an active power no load detection.
Rev. 0 | Page 38 of 128
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