参数资料
| 型号： | ADF4351BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/28页 |
| 文件大小： | 0K |
| 描述： | IC SYNTH PLL VCO 32LFCSP |
| 标准包装： | 1 |
| 类型： | 扇出配送，分数-N，整数-N，时钟/频率合成器（RF） |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:3 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 4.4GHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP（5x5） |
| 包装： | 托盘 |
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Data Sheet
ADF4351
Rev. 0 | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
CLK
2
DATA
3
LE
4
CE
5
SW
6
7
24
VREF
23
VCOM
22
21
20
19
18
17
8
S
DV
DD
ADF4351
TOP VIEW
(Not to Scale)
9
AG
ND
10
AV
DD
11
RE
F
IN
12
DG
ND
13
DV
DD
14
15
16
32
31
30
29
28
SD
G
ND
27
26
25
PIN 1
INDICATOR
VP
CPOUT
CPGND
M
UX
O
UT
RSET
RF
O
UT
A+
RF
O
UT
B+
RF
O
UT
B
RF
O
UT
A
V
CO
VTUNE
AGNDVCO
TEMP
P
DB
RF
LD
A
G
NDV
CO
VVCO
NOTES
1. THE LFCSP HAS AN EXPOSED PAD THAT
MUST BE CONNECTED TO GND.
09800-
003
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CLK
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
2
DATA
Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high
impedance CMOS input.
3
LE
Load Enable. When LE goes high, the data stored in the 32-bit shift register is loaded into the register that is
selected by the three control bits. This input is a high impedance CMOS input.
4
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.
A logic high on this pin powers up the device, depending on the status of the power-down bits.
5
SW
Fast Lock Switch. A connection should be made from the loop filter to this pin when using the fast lock mode.
6
V
P
Charge Pump Power Supply. V
P must have the same value as AVDD. Place decoupling capacitors to the ground
plane as close to this pin as possible.
7
CP
OUT
Charge Pump Output. When enabled, this output provides ±I
CP to the external loop filter. The output of the
loop filter is connected to V
TUNE to drive the internal VCO.
8
CP
GND
Charge Pump Ground. This output is the ground return pin for CP
OUT.
9
AGND
Analog Ground. Ground return pin for AV
DD.
10
AV
DD
Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Place decoupling capacitors to the analog ground
plane as close to this pin as possible. AV
DD must have the same value as DVDD.
11, 18, 21
A
GNDVCO
VCO Analog Ground. Ground return pins for the VCO.
12
RF
OUTA+
VCO Output. The output level is programmable. The VCO fundamental output or a divided-down version is
available.
13
RF
OUTA
Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided-
down version is available.
14
RF
OUTB+
Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a divided-down
version is available.
15
RF
OUTB
Complementary Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a
divided-down version is available.
16, 17
V
VCO
Power Supply for the VCO. This pin ranges from 3.0 V to 3.6 V. Place decoupling capacitors to the analog
ground plane as close to these pins as possible. V
VCO must have the same value as AVDD.
19
TEMP
Temperature Compensation Output. Place decoupling capacitors to the ground plane as close to this pin as
possible.
20
V
TUNE
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP
OUT
output voltage.
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| ADF4351BCPZ-RL7 | 功能描述:IC SYNTH PLL VCO 32LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
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