参数资料
| 型号： | ADM1025ARQZ-R7 |
| 厂商： | ON Semiconductor |
| 文件页数： | 14/19页 |
| 文件大小： | 0K |
| 描述： | IC MONITOR SYS/VOLT 5CH 16QSOP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi Product Obsolescence 11/Feb/2009 |
| 标准包装： | 1,000 |
| 应用： | PC，PDA |
| 接口： | I²C |
| 电源电压： | 3 V ~ 5.5 V |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
ADM1025, ADM1025A
http://onsemi.com
4
Table 4. ELECTRICAL CHARACTERISTICS (continued)
(TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted)
Parameter
Unit
Max
Typ
Min
Test Conditions/Comments
OPEN-DRAIN DIGITAL OUTPUTS (ADD, RST, INT, NTO)
Output Low Voltage, VOL
IOUT = 6.0 mA, VCC = 3 V
0.4
V
High Level Output Current, IOH
VOUT = VCC, VCC = 3 V
0.1
1.0
mA
RST Pulsewidth
VOUT = VCC, VCC = 3 V
20
45
ms
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL
IOUT = –6.0 mA, VCC = 3 V
0.4
V
High Level Output Leakage Current, IOH
VOUT = VCC
0.1
1.0
mA
SERIAL BUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH
2.1
V
Input Low Voltage, VIL
0.8
V
Hysteresis
500
mV
DIGITAL INPUT LOGIC LEVELS (ADD, VID0VID4, NTI) (Note 5)
VID0VID3 Input Resistance
ADM1025 Only
100
V
VID4 Input Resistance
ADM1025
ADM1025A
300
100
V
2.1
V
0.8
V
DIGITAL INPUT LEAKAGE CURRENT
Input High Current, IIH
VIN = VCC
–1.0
mA
Input Low Current, IIL
VIN = 0
1.0
mA
Input Capacitance, CIN
5
pF
Conversion Cycle Time
637
ms
SERIAL BUS TIMING
Clock Frequency, fSCLK
See Figure 2 for All Parameters.
400
kHz
Glitch Immunity, tSW
50
ns
Bus Free Time, tBUF
1.3
ms
Start Setup Time, tSU; STA
600
ns
Start Hold Time, tHD; STA
600
ns
Stop Condition Setup Time, tSU; STO
600
ns
SCL Low Time, tLOW
1.3
ms
SCL High Time, tHIGH
0.6
ms
SCL, SDA Rise Time, tR
300
ns
SCL, SDA Fall Time, tF
300
ns
Data Setup Time, tSU; DAT
100
ns
Data Hold Time, tHD; DAT
300
ns
1. All voltages are measured with respect to GND, unless otherwise specified.
2. Typicals are at TA = 25C and represent the most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V.
3. TUE (Total Unadjusted Error) includes Offset, Gain, and Linearity errors of the ADC, multiplexer, and on-chip input attenuators, including
an external series input protection resistor value between zero and 1 kW.
4. Total monitoring cycle time is nominally 114.4 ms. Monitoring Cycle consists of 6 Voltage + 1 Internal Temperature + 1 External Temperature
readings.
5. ADD is a three-state input that may be pulled high, low or left open-circuit.
6. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge.
NOTE: Specifications subject to change without notice.
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