参数资料
| 型号： | ADM1025ARQZ-R7 |
| 厂商： | ON Semiconductor |
| 文件页数： | 5/19页 |
| 文件大小： | 0K |
| 描述： | IC MONITOR SYS/VOLT 5CH 16QSOP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi Product Obsolescence 11/Feb/2009 |
| 标准包装： | 1,000 |
| 应用： | PC，PDA |
| 接口： | I²C |
| 电源电压： | 3 V ~ 5.5 V |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
ADM1025, ADM1025A
http://onsemi.com
13
The worst such accident would be connecting 0 V to 12 V
a total of 12 V difference. With the series resistors, this
would draw a maximum current of approximately 12 mA.
Layout and Grounding
Analog inputs will provide best accuracy when referred to
a clean ground. A separate, low impedance ground plane for
analog ground, which provides a ground point for the
voltage dividers and analog components, will provide best
performance but is not mandatory.
The power supply bypass, the parallel combination of
10
mF (electrolytic or tantalum) and 0.1 mF (ceramic) bypass
capacitors connected between Pin 9 and ground, should also
be
located
as
close
as
possible
to
the
ADM1025/ADM1025A.
RST/INT Output
As previously mentioned, Pin 16 is a multifunction pin.
Its state after power-on is latched to set the lowest two bits
of the serial bus address. During NAND tree board-level
connectivity testing, it functions as the output of the NAND
tree. It may also be used as a reset output, or as an interrupt
output for out-of-limit temperature/voltage events.
Pin 16 is programmed as a reset output by clearing Bit 0
of the Test Register and setting Bit 7 of the VID Register. A
low going, 20 ms, reset output pulse can then be generated
by setting Bit 4 of the Configuration Register.
If Bit 7 of the VID Register is cleared, Pin 16 can be
programmed as an interrupt output for out-of-limit
temperature/voltage events (INT). Desired interrupt
operation is achieved by changing the values of Bits 1 and
0 of the Test Register as shown in Table 8. Note, however,
that Bits 2 to 7 of the Test Register must be zeros (not don’t
cares). If, for example, INT is programmed for thermal and
voltage interrupts, then if any temperature or voltage
measurement goes outside its respective high or low limit,
the INT output will go low. It will remain low until Status
Register 1 is read, when it will be cleared. If the temperature
or voltage remains out of limit, INT will be reasserted on the
next monitoring cycle. INT can also be cleared by issuing an
Alert Response Address Call.
Table 8. CONTROLLING THE OPERATION OF INT
Test Register
Function
Bit 1
Bit 0
0
Interrupts Disabled
0
1
Thermal Interrupt Only
1
0
Voltage Interrupt Only
1
Voltage and Thermal Interrupts
Note that Bit 7 of VID register should be zero, and that
Bits 2 to 7 of Test Register must be zeros.
When Pin 16 is used as a RST or INT output, it is
open-drain and requires an external pull-up resistor. This
will restrict the address function on Pin 16 to being high at
power-up. If the RST or INT function is required and two
ADM1025/ADM1025As are to be used on the same serial
bus, A1/A0 can be set to 10 by using a high value pull-up on
Pin 16 (100 k
W or greater). This will not override the
“floating” condition of ADD during power-up.
Note, however, that the RST/INT outputs of two or more
devices cannot be wire-OR’d, since the devices would then
have the same address. If the RST/INT outputs need to be
connected to a common interrupt line, they can be OR’d
together using the circuit of Figure 16.
If the RST or INT functionality is not required, a third
address may be used by setting A1/A0 to 00 by using a 1 k
W
pull-down resistor on Pin 16. Note that this address should
not be used if RST or INT is required, since using this
address will cause the device to appear to be generating
resets or interrupts, since Pin 16 will be permanently tied
low.
Figure 16. Using Two ADM1025/ADM1025As on the Same Bus with a Common Interrupt
VCC
R5
4.7 kW
R2
470 kW
R1
1 kW
OPEN-COLLECTOR
AND GATE
RST OR INT
A1/A0 01
A1/A0 10
SDA
SCL
ADD/RST/INT/NTO
ADM1025/
ADM1025A
No.1
SDA
SCL
ADD/RST/INT/NTO
ADM1025/
ADM1025A
No.2
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