参数资料
| 型号： | ADM1025ARQZ-R7 |
| 厂商： | ON Semiconductor |
| 文件页数： | 6/19页 |
| 文件大小： | 0K |
| 描述： | IC MONITOR SYS/VOLT 5CH 16QSOP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi Product Obsolescence 11/Feb/2009 |
| 标准包装： | 1,000 |
| 应用： | PC，PDA |
| 接口： | I²C |
| 电源电压： | 3 V ~ 5.5 V |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
ADM1025, ADM1025A
http://onsemi.com
14
Generating an SMBALERT
The INT output can be used as an interrupt output or can
be used as an SMBALERT. One or more INT outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s INT line goes low, the following
procedure occurs:
1. SMBALERT is pulled low.
2. Master initiates a read operation and sends the
Alert Response Address (ARA = 0001 100). This
is a general call address that must not be used as a
specific device address.
3. The device whose INT output is low responds to
the Alert Response Address, and the master reads
its device address. The address of the device is
now known and it can be interrogated in the usual
way.
4. If more than one device’s INT output is low, the
one with the lowest device address will have
priority, in accordance with normal SMBus
arbitration.
5. Once the ADM1025/ADM1025A has responded to
the Alert Response Address, it will reset its INT
output; however, if the error condition that caused
the interrupt persists, INT will be reasserted on the
next monitoring cycle.
NAND Tree Tests
A NAND tree is provided in the ADM1025/ADM1025A
for Automated Test Equipment (ATE) board level
connectivity testing. The device is placed into NAND Test
Mode by powering up with Pin 9 (D/NTI) held high. This
pin is automatically sampled after power-up, and if it is
connected high, the NAND test mode is invoked.
In NAND test mode, all digital inputs may be tested as
illustrated below. ADD/RST/INT/NTO will become the
NAND test output pin.
To perform a NAND tree test, all pins are initially driven
low. The test vectors set all inputs low, then one-by-one
toggle them high (keeping them high). Exercising the test
circuit with this “walking one” pattern, starting with the
input closest to the output of the tree, cycling toward the
farthest, causes the output of the tree to toggle with each
input change. Allow for a typical propagation delay of
500 ns. The structure of the NAND tree is shown in
Figure 17.
Figure 17. NAND Tree
ADD/RST/INT/
NTO
SDA
SCL
VID0
VID1
VID2
VID3
NOTE: If any of the inputs shown in Figure 17 are unused, they
should not be connected directly to ground but via a resistor
such as 10 kW. This will allow the ATE to drive every input
high so that the NAND tree test can be properly carried out.
Refer to Table 20 for Test Vectors.
Using the ADM1025/ADM1025A
Power-on Reset
When power is first applied, the ADM1025/ADM1025A
performs a “power-on reset” on several of its registers.
Registers whose power-on values are not shown have
power-on conditions that are indeterminate. Value and limit
registers are reset to 00h on power-up. The ADC is inactive.
In most applications, usually the first action after power-on
would be to write limits into the Limit Registers.
Power-on reset clears or initializes the following registers
(the initialized values are shown in Table 10):
Configuration Register
Status Registers #1 and #2
VID03 Register
VID4 Register
Test Register
Initialization
Configuration Register Initialization performs a similar,
but not identical, function to power-on reset.
Configuration Register Initialization is accomplished by
setting Bit 7 of the Configuration Register high. This bit
automatically clears after being set.
Using the Configuration Register
Control of the ADM1025/ADM1025A is provided
through the configuration register. The Configuration
Register
is
used
to
start
and
stop
the
ADM1025/ADM1025A, program the operating modes of
Pins 11 and 16, and provide the initialization function
described above.
Bit 0 of the Configuration Register controls the
monitoring loop of the ADM1025/ADM1025A. Setting
Bit 0 low stops the monitoring loop and puts the
ADM1025/ADM1025A into a low power mode thereby
reducing power consumption. Serial bus communication is
still
possible
with
any
register
in
the
ADM1025/ADM1025A while in low power mode. Setting
Bit 0 high starts the monitoring loop.
Bit 4 of the Configuration Register causes a low going
20 ms (typ) pulse at the RST pin (Pin 16) when set. This bit
is self-clearing.
Bit 5 of the Configuration Register selects the operating
mode of Pin 11 between the default of 12 V analog input
(Bit 5 = 0) and VID4 (Bit 5 = 1).
Bit 7 of the Configuration Register is used to start a
Configuration Register Initialization when it is set to 1.
Using the Offset Register
This register contains a twos complement value that is
added (or subtracted if the number is negative) to either the
internal or external temperature reading. Note that the
default value in the offset register is zero, so zero is always
added to the temperature reading. The offset register is
configured for the external temperature channel by default.
It may be switched to the internal channel by setting Bit 0 of
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