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参数资料
| 型号： | ADM1066ASUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 27/32页 |
| 文件大小： | 0K |
| 描述： | IC SEQUENCER/SUPERVISOR 48TQFP |
| 标准包装： | 2,000 |
| 系列： | Super Sequencer® |
| 类型： | 序列发生器 |
| 监视电压数目： | 12 |
| 输出： | 可编程 |
| 电压 - 阀值： | 可调节/可选择 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 带卷 (TR) |
| 配用： | EVAL-ADM1066TQEBZ-ND - BOARD EVALUATION FOR ADM1066TQ |
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ADM1066
The device also has several identification registers (read-only)
that can be read across the SMBus. Table 12 lists these registers
with their values and functions.
Table 12. Identification Register Values and Functions
All other devices on the bus remain idle while the selected device
waits for data to be read from or written to it. If the R/W bit is a 0,
the master writes to the slave device. If the R/W bit is a 1, the
master reads from the slave device.
Name
MANID
Address
0xF4
Value
0x41
Function
Manufacturer ID for Analog
Step 2
Data is sent over the serial bus in sequences of nine clock pulses:
Devices
eight bits of data followed by an acknowledge bit from the slave
REVID
MARK1
MARK2
0xF5
0xF6
0xF7
0x02
0x00
0x00
Silicon revision
Software brand
Software brand
device. Data transitions on the data line must occur during the
low period of the clock signal and remain stable during the high
period because a low-to-high transition when the clock is high
General SMBus Timing
general read and write operations using the SMBus. The SMBus
specification defines specific conditions for different types of
read and write operations, which are discussed in the Write
Operations and the Read Operations sections.
The general SMBus protocol operates as follows:
Step 1
The master initiates data transfer by establishing a start condition,
defined as a high-to-low transition on the serial data line SDA,
while the serial clock line SCL remains high. This indicates that
a data stream follows. All slave peripherals connected to the serial
bus respond to the start condition and shift in the next eight bits,
consisting of a 7-bit slave address (MSB first) plus an R/W bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 = write,
1 = read).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the acknowledge
bit, and by holding it low during the high period of this clock pulse.
could be interpreted as a stop signal. If the operation is a write
operation, the first data byte after the slave address is a command
byte. This command byte tells the slave device what to expect next.
It may be an instruction telling the slave device to expect a block
write, or it may be a register address that tells the slave where
subsequent data is to be written. Because data can flow in only
one direction, as defined by the R/W bit, sending a command
to a slave device during a read operation is not possible. Before
a read operation, it may be necessary to perform a write operation
to tell the slave what sort of read operation to expect and/or the
address from which data is to be read.
Step 3
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line high
during the 10th clock pulse to assert a stop condition. In read
mode, the master device releases the SDA line during the low
period before the ninth clock pulse, but the slave device does
not pull it low. This is known as a no acknowledge. The master
then takes the data line low during the low period before the
10th clock pulse and then high during the 10th clock pulse to
assert a stop condition.
1
9
1
9
SCL
SDA
0
1
1
0
1
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
START BY
MASTER
FRAME 1
SLAVE ADDRESS
ACK. BY
SLAVE
FRAME 2
COMMAND CODE
ACK. BY
SLAVE
SCL
(CONTINUED)
1
9
1
9
SDA
(CONTINUED)
D7
D6
D5
D4 D3 D2
FRAME 3
DATA BYTE
D1
D0
ACK. BY
SLAVE
D7
D6
D5
D4 D3 D2
FRAME N
DATA BYTE
D1
D0
ACK. BY
SLAVE
STOP
BY
MASTER
Figure 36. General SMBus Write Timing Diagram
Rev. E | Page 27 of 32
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| ADM1066ASUZ-REEL7 | 功能描述:IC SEQUENCER/SUPERVISOR 48TQFP RoHS:是 类别:集成电路 (IC) >> PMIC - 监控器 系列:Super Sequencer® 标准包装:1 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:开路漏极或开路集电极 复位:高有效 复位超时:- 电压 - 阀值:1.8V 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:6-TSOP（0.059"，1.50mm 宽）5 引线 供应商设备封装:5-TSOP 包装:剪切带 (CT) 其它名称:NCP301HSN18T1GOSCT |
| ADM1067 | 制造商:AD 制造商全称:Analog Devices 功能描述:Super Sequencer with Open-Loop Margining DACs |
| ADM1067ACP | 制造商:Analog Devices 功能描述:Sequencer 40-Pin LFCSP EP |
| ADM1067ACP-REEL | 制造商:Analog Devices 功能描述:Sequencer 40-Pin LFCSP EP T/R |
| ADM1067ACP-REEL7 | 制造商:Analog Devices 功能描述:Sequencer 40-Pin LFCSP EP T/R |
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