参数资料
型号: ADM1069ASTZ
厂商: Analog Devices Inc
文件页数: 3/32页
文件大小: 0K
描述: IC SUPERVISOR/SEQUENCER 32-LQFP
标准包装: 1
系列: Super Sequencer®
类型: 序列发生器
监视电压数目: 8
输出: 可编程
电压 - 阀值: 8 种可选阀值组合
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-LQFP
供应商设备封装: 32-LQFP(7x7)
包装: 托盘
产品目录页面: 788 (CN2011-ZH PDF)
配用: EVAL-ADM1069LQEBZ-ND - BOARD EVALUATION FOR ADM1069LQ

ADM1069
Supply margining can be performed with a minimum of external
components. The margining loop can be used for in-circuit
testing of a board during production (for example, to verify
board functionality at ?5% of nominal supplies), or it can be
used dynamically to accurately control the output voltage of
a dc-to-dc converter.
The device also provides up to eight programmable inputs for
monitoring undervoltage faults, overvoltage faults, or out-of-
window faults on up to eight supplies. In addition, there are eight
programmable outputs that can be used as logic enables. Six of
these programmable outputs can also provide up to a 12 V output
for driving the gate of an N-FET that can be placed in the path
of a supply.
DETAILED BLOCK DIAGRAM
The logical core of the device is a sequencing engine (SE). This
state machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs, based
on the condition of the inputs.
The ADM1069 is controlled via configuration data that can be
programmed into an EEPROM. The entire configuration can
be programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.
ADM1069
REFIN
REFOUT
12-BIT
SAR ADC
REFGND SDA SCL A1
SMBus
VREF
INTERFACE
DEVICE
CONTROLLER
A0
OSC
EEPROM
GPI SIGNAL
CONDITIONING
CONFIGURABLE
OUTPUT DRIVER
(HV)
PDO1
VX1
VX2
SFD
PDO2
PDO3
PDO4
PDO5
VX3
VX4
GPI SIGNAL
CONDITIONING
SFD
SEQUENCING
ENGINE
CONFIGURABLE
OUTPUT DRIVER
(HV)
PDO6
VP1
VP2
SELECTABLE
ATTENUATOR
SFD
CONFIGURABLE
OUTPUT DRIVER
(LV)
PDO7
VP3
VH
SELECTABLE
ATTENUATOR
SFD
CONFIGURABLE
OUTPUT DRIVER
(LV)
PDO8
AGND
PDOGND
VDDCAP
VDD
ARBITRATOR
REG 5.25V
CHARGE PUMP
V OUT
DAC
V OUT
DAC
GND
VCCP
DAC1
DAC2
DAC3
DAC4
Figure 2. Detailed Block Diagram
Rev. C | Page 3 of 32
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