- 您现在的位置：买卖IC网 > PDF目录375258 > ADM1192-1ARMZ-R7 (ANALOG DEVICES INC) Digital Power Monitor with Clear Pin and ALERT Output PDF资料下载
参数资料
| 型号： | ADM1192-1ARMZ-R7 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 电源管理 |
| 英文描述： | Digital Power Monitor with Clear Pin and ALERT Output |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO10 |
| 封装： | LEAD FREE, MO-187BA, MSOP-10 |
| 文件页数： | 10/20页 |
| 文件大小： | 274K |
| 代理商： | ADM1192-1ARMZ-R7 |
ADM1192
VOLTAGE AND CURRENT READBACK
The ADM1192 contains the components to allow voltage and
current readback over an Inter-IC (I
2
C) bus. The voltage output
of the current sense amplifier and the voltage on the VCC pin
are fed into a 12-bit ADC via a multiplexer. The device can be
instructed to convert voltage and/or current at any time during
operation via an I
2
C command. When all conversions are
complete, the voltage and/or current values can be read out to
12-bit accuracy in two or three bytes.
Rev. 0 | Page 10 of 20
SERIAL BUS INTERFACE
Control of the ADM1192 is carried out via the serial system
management bus (I
2
C). This interface is compatible with I
2
C
fast mode (400 kHz maximum). The ADM1192 is connected to
this bus as a slave device, under the control of a master device.
IDENTIFYING THE ADM1192 ON THE I
2
C BUS
The ADM1192 has a 7-bit serial bus slave address. When the
device powers up, it does so with a default serial bus address.
The five MSBs of the address are set to 01011; the two LSBs are
determined by the state of the ADR pin. There are four different
configurations available on the ADR pin that correspond to four
different I
2
C addresses for the two LSBs (see Table 5). This
scheme allows four ADM1192 devices to operate on a single I
2
C.
Table 5. Setting I
2
C Addresses via the ADR Pin
ADR Configuration
Low state
Resistor to GND
Floating (unconnected)
High state
Address
0x68
0x69
0x6A
0x6B
GENERAL I
2
C TIMING
Figure 18 and Figure 19 show timing diagrams for general read
and write operations using the I
2
C. The I
2
C specification defines
conditions for different types of read and write operations, which
are discussed later. The general I
2
C protocol operates as follows:
1.
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line, SDA, while the serial clock line, SCL, remains high.
This indicates that a data stream follows. All slave peripherals
connected to the serial bus respond to the start condition
and shift in the next eight bits, consisting of a 7-bit slave
address (MSB first) plus an R/W bit that determines the
direction of the data transfer; that is, whether data is written
to or read from the slave device (0 = write, 1 = read).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the
low period before the ninth clock pulse, known as the
acknowledge bit, and holding it low during the high period of
this clock pulse. All other devices on the bus now remain
idle while the selected device waits for data to be read from
it or written to it. If the R/W bit is 0, the master writes to
the slave device. If the R/W bit is 1, the master reads from
the slave device.
2.
Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period because a low-to-
high transition when the clock is high can be interpreted
as a stop signal.
If the operation is a write operation, the first data byte
after the slave address is a command byte. This tells the
slave device what to expect next. It can be an instruction,
such as telling the slave device to expect a block write, or
it can be a register address that tells the slave where subse-
quent data is to be written.
Because data can flow in only one direction, as defined by
the R/W bit, it is not possible to send a command to a
slave device during a read operation. Before doing a read
operation, it may first be necessary to do a write operation
to tell the slave what sort of read operation to expect
and/or the address from which data is to be read.
3.
When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the 10th clock pulse to assert a
stop condition. In read mode, the master device releases
the SDA line during the low period before the ninth clock
pulse, but the slave device does not pull it low. This is known
as a no acknowledge. The master then takes the data line
low during the low period before the 10th clock pulse, then
high during the 10th clock pulse to assert a stop condition.
相关PDF资料 |
PDF描述 |
|---|---|
| ADM14185E | RS-232 Line Drivers/Receivers(±15kV ESD保护,RS-232线驱动器/接收器) |
| ADM14196E | RS-232 Line Drivers/Receivers(±15kV ESD保护,RS-232线驱动器/接收器) |
| ADM208E | RS-232 Line Drivers/Receivers(15kV ESD保护,RS-232线驱动器/接收器) |
| ADM209 | +5 V Powered CMOS RS-232 Drivers/Receivers(CMOS RS-232驱动器/接收器) |
| ADM213 | +5 V Powered CMOS RS-232 Drivers/Receivers(CMOS RS-232驱动器/接收器) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADM1192ARMZ-R7 | 功能描述:IC PWR MONITOR DGTL ALERT 10MSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 电源管理 - 专用 系列:- 应用说明:Ultrasound Imaging Systems Application Note 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:37 系列:- 应用:医疗用超声波成像，声纳 电流 - 电源:- 电源电压:2.37 V ~ 6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:56-WFQFN 裸露焊盘 供应商设备封装:56-TQFN-EP（8x8） 包装:管件 |
| ADM1232 | 制造商:AD 制造商全称:Analog Devices 功能描述:Microprocessor Supervisory Circuit |
| ADM1232_08 | 制造商:AD 制造商全称:Analog Devices 功能描述:Microprocessor Supervisory Circuit |
| ADM1232A | 制造商:AD 制造商全称:Analog Devices 功能描述:Microprocessor Supervisory Circuit |
| ADM1232AAN | 制造商:AD 制造商全称:Analog Devices 功能描述:Microprocessor Supervisory Circuit |
发布紧急采购，3分钟左右您将得到回复。