
ADM1192
WRITE EXTENDED BYTE
In the write extended byte operation, the master device writes
to one of the three extended registers of the slave device, as follows:
Rev. 0 | Page 13 of 20
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address, followed by the
write bit (low).
3.
The addressed slave device asserts an acknowledge on SDA.
4.
The master sends the register address byte. The MSB of this
byte is set to 1 to indicate an extended register write. The two
LSBs indicate which of the three extended registers are to be
written to (see Table 8). All other bits should be set to 0.
5.
The slave asserts an acknowledge on SDA.
6.
The master sends the command byte. The command byte
is identified by an MSB = 0. An MSB = 1 indicates an
extended register write.
7.
The slave asserts an acknowledge on SDA.
8.
The master asserts a stop condition on SDA to end the
transaction.
S
ASLAVE
REGISTER
ADDRESS
A P
REGISTER
DATA
A
1
2
3
4
5
6
7 8
0
Figure 23. Write Extended Byte
Table 9, Table 10, and Table 11 give details of each extended
register.
Table 8. Extended Register Addresses
A6
A5
A4
A3
A2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A1
0
1
1
A0
1
0
1
Extended Register
ALERT_EN
ALERT_TH
CONTROL
Table 9. ALERT_EN Register Operations
Bit
Default
Name
0
0
EN_ADC_OC1
Function
Enabled if a single ADC conversion on the I channel has exceeded the threshold set in the ALERT_TH
register.
Enabled if four consecutive ADC conversions on the I channel have exceeded the threshold set in the
ALERT_TH register.
Enables the OC_ALERT register. If an overcurrent condition is present and the TIMER pin has charged to
1.3 V, the OC_ALERT register captures and latches this condition.
Enables an alert if the HS operation is turned off by an operation that writes the SWOFF bit high. This
allows software override of the ALERT output and turns on a P-channel FET controlled by ALERT.
Clears the OC_ALERT and ADC_ALERT status bits in the status register. These may immediately reset if
the source of the alert has not been cleared or disabled with the other bits in this register. This bit self-
clears to 0 after the status register bits have been cleared.
1
0
EN_ADC_OC4
2
1
EN_OC_ALERT
3
0
EN_OFF_ALERT
4
0
CLEAR
Table 10. ALERT_TH Register Operations
Bit
Default
Function
7:0
FF
The ALERT_TH register sets the current level at which an alert occurs. Defaults to ADC full scale. The ALERT_TH 8-bit
number corresponds to the top eight bits of the current channel data.
Table 11. CONTROL Register Operations
Bit
Default
Name
0
0
SWOFF
Function
Forces the ALERT pin to deassert. Can be active only if the EN_OFF_ALERT bit is high (see Table 9).