参数资料
型号: ADM8690ANZ
厂商: Analog Devices Inc
文件页数: 7/24页
文件大小: 0K
描述: IC SUPERVISOR MPU 4.65V 8DIP
标准包装: 50
类型: 备用电池电路
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 最小为 35 ms
电压 - 阀值: 4.65V
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件

Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADM8690/ADM8691/ADM8695
V BATT 1
V OUT 2
16 RESET
15 RESET
V CC 3
GND 4
ADM8691/
ADM8695
14 WDO
13 CE IN
V OUT 1
V CC 2
GND 3
PFI 4
ADM8690
TOP VIEW
(Not to Scale)
8 V BATT
7 RESET
6 WDI
5 PFO
BATT ON 5
LOW LINE 6
OSC IN 7
OSC SEL 8
TOP VIEW
(Not to Scale)
12 CE OUT
11 WDI
10 PFO
9 PFI
Figure 3. ADM8690 Pin Configuration,
8-Lead PDIP and 8-Lead SOIC_N
Table 4. Pin Function Descriptions
Pin No.
Figure 4. ADM8691 / ADM8695 Pin Configuration, 16-Lead PDIP,
16-Lead SOIC_N, 16-Lead SOIC_W, and 16-Lead TSSOP
8-Lead
8
16-Lead
1
Mnemonic
V BATT
Description
Backup Battery Input. V BATT or V CC is internally switched to V OUT , depending on which is at the
highest potential.
1
2
V OUT
Output Voltage. V CC or V BATT is internally switched to V OUT , depending on which is at the highest
potential. V OUT can supply up to 100 mA to power CMOS RAM. Connect V OUT to V CC if V OUT and V BATT
are not used.
2
3
V CC
Power Supply Input. 5 V nominal. V CC or V BATT is internally switched to V OUT , depending on which is
at the highest potential.
3
N/A
4
5
GND
BATT ON
Ground. This is the 0 V ground reference for all signals.
Logic Output. BATT ON goes high when V OUT is internally switched to the V BATT input. It goes low
when V OUT is internally switched to V CC . The output typically sinks 35 mA and can directly drive the
base of an external PNP transistor to increase the output current above the 100 mA rating of V OUT .
N/A
6
LOW LINE
Logic Output. LOW LINE goes low when V CC falls below the reset threshold. It returns high as
soon as V CC rises above the reset threshold.
N/A
7
OSC IN
Oscillator Logic Input. When OSC SEL is low, OSC IN can be driven by an external clock signal, or
an external capacitor can be connected between OSC IN and GND. This sets both the reset active
pulse timing and the watchdog timeout period (see Table 5 and Figure 17 through Figure 20).
When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is
fixed at 50 ms typical ( ADM8691 ) or 200 ms typical ( ADM8695 ). In this mode, the OSC IN pin
selects either the fast (100 ms) or slow (1.6 sec) watchdog timeout period. In both modes, the
timeout period immediately after a reset is 1.6 sec typical.
N/A
8
OSC SEL
Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal
oscillator sets the reset active time and watchdog timeout period. When OSC SEL is low, the
external oscillator input, OSC IN, is enabled (see Table 5). OSC SEL has a 5 μA internal pull-up.
4
9
PFI
Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less than
1.3 V, PFO goes low. Connect PFI to GND or V OUT when not used.
5
10
PFO
Power-Fail Output. PFO is the output of the power-fail comparator. It goes low when PFI is less
than 1.3 V. The comparator is turned off and PFO goes low when V CC is below V BATT .
6
11
WDI
Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than
the watchdog timeout period, RESET pulses low and WDO goes low. The timer is reset with each
transition on the WDI line. The watchdog timer can be disabled if WDI is left floating or is driven
to midsupply.
N/A
12
CE OUT
Logic Output. CE OUT is a gated version of the CE IN signal. CE OUT tracks CE IN when V CC is above the reset
threshold. If V CC is below the reset threshold, CE OUT is forced high. See Figure 21 and Figure 22 .
N/A
N/A
13
14
CE IN
WDO
Logic Input. Input to the CE gating circuit. When not in use, connect this pin to GND or V OUT .
Logic Output. The watchdog output, WDO, goes low if WDI remains either high or low for longer
than the watchdog timeout period. WDO is set high by the next transition at WDI. If WDI is
unconnected or at midsupply, the watchdog timer is disabled and WDO remains high. WDO also
goes high when LOW LINE goes low.
Rev. C | Page 7 of 24
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