参数资料
型号: ADMC201AP
厂商: ANALOG DEVICES INC
元件分类: 微控制器/微处理器
英文描述: Motion Coprocessor
中文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PQCC68
封装: PLASTIC, LCC-68
文件页数: 11/15页
文件大小: 146K
代理商: ADMC201AP
ADMC201
REV. B
11
REGISTER ADDRESSING
Four address lines (A0 through A3) are used in conjunction
with the control lines (
CS,
WR
,
RD
,) to select registers 0
through 15. The
CS
and
RD
control lines are active low. The
registers are given symbolic names.
Table II.
Pin
Function
CS
Enables the ADMC201 register interface
(connect via chip select logic-active low)
Places data from the internal register onto the
data bus
Loads the internal register with data on the
data bus on its positive edge
RD
WR
PHIP1/2/3
The inputs for reverse vector transforma-
tion (Clarke and Park).
These registers contain the results
of the Clarke transformation that
are the inputs to the reverse Park rotation.
VX, VY contain the results of the forward
Park rotation.
RHOP is the angle used during the
forward vector transformation. Writing to
the RHOP register causes the forward
rotation to start based on values in
RHOP, VD and VQ registers.
RHO is the angle used during the reverse
vector transformation. Writing to this
register starts the reverse rotation using
the values in the RHO, PHIP1/2/3
registers.
RHO and RHOP are unsigned ratios of
360
°
. For example, 45 degrees would be
45/360
×
2
12
.
Write to this register to change the
digital outputs and read from it to
determine the state of digital inputs.
This register is used to configure the
digital I/O as input or output and to
enable interrupt on change of state.
IX/IY
VX, VY
RHOP
RHO
PIODATA
PIOCTRL
DESCRIPTION OF THE REGISTERS
All unspecified register locations are reserved.
SYSCTRL
System Control Register (See Tables V,
VI, VII).
SYSSTAT
System Status Register (See Table VII).
ADCU
These registers contain the results from
ADCV
the first three analog input channels
ADCW
U, V, and W. The output data format
is twos complement and, therefore, Bit 0
is always zero as the A/D converter
has 11-bit resolution.
ADCAUX
This register contains the conversion result
of the auxiliary channels AUX0, AUX1,
AUX2 or AUX3.
PWMTM
PWM Master Switching Period
PWMCHA
PWM Channel A On-Time
PWMCHB
PWM Channel B On-Time
PWMCHC
PWM Channel C On-Time
PWMDT
PWM Programmable Deadtime Value
PWMPD
PWM Programmable Pulse Deletion Value
ID/IQ
These are the results of the reverse
rotation (torque and flux components).
PHV1/2/3
These are the results from the forward
Clarke Transformation.
EN
ADDRESS
DECODE
V
DD
IS
INTn
STRB
R/W
CLKOUT1
D0
D15
A0
A15
TMS320C20
TMS320C25
TMS320C25-50
CS
IRQ
RD
WR
CLK
D0
D11
A0
A3
ADMC201
ADDRESS BUS
DATA BUS
Figure 12. TI Second Generation Devices TMS320C20/
C25/C25
50
In the case of the ADSP-2171/2181, the system clock is inter-
nally scaled, a 10 MHz system clock will derive a 20 MHz
CLKOUT. In the case of the TMS320C2X, the CLKOUT1
signal is derived from the system clock divided by a factor of 4,
consequently a 50 MHz TMS320C25-50 will derive a
12.5 MHz CLKOUT1 for use by the ADMC201.
Note: a pull-up resistor is required on the IRQ (Pin 18) output
from the ADMC201. The STOP (Pin 47) must be tied low if
not in use.
相关PDF资料
PDF描述
ADMC201 Motion Coprocessor(动作协处理器)
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