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参数资料
| 型号： | ADMC201AP |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Motion Coprocessor |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 13/15页 |
| 文件大小： | 146K |
| 代理商： | ADMC201AP |
ADMC201
REV. B
–
13
–
Table VII. SYSCTRL Analog Input Channel Selection
Bit 3
Bit 4
Channels Converted
Mode
0
0
1
1
0
1
0
1
V, W (Default)
V, W, AUX
U, V, W
U, V, W, AUX
Two-/Three-Phase
Two-/Three-Phase
Three-/Three-Phase
Three-/Three-Phase
Bit 0, 1 Auxiliary Channel Selection.
Bit 3
Channel U Conversion Enable. If Bit 3 is set to 1, then
Channel U will be converted along with V, W and/or
AUX. This bit selects three-/three-phase mode.
Bit 4
Aux Channel Conversion Enable. If Bit 4 is set to
1, then the AUX input will be converted along with
the channels V, W and/or U.
Bit 5
If Bit 5 = 1, then the external clock will be divided by
two to derive the system clock. If the external clock
frequency is greater than 12.5 MHz, then this bit must
be set.
Bit 6
Park Interrupt Enable. This bit allows interrupts to
be generated when the Park rotation is completed.
Bit 7
ADC Interrupt Enable. This bit allows interrupts to
be generated when the analog-to-digital conversion
process is complete.
Bit 8
IRQ
Pin Format
—
Edge or Level Interrupt Selection.
If Bit 8 is set to 0, then an interrupt will cause a
pulse of one system clock to be generated on the
IRQ
pin. If Bit 8 is set to 1, then an interrupt
causes the
IRQ
output to go LOW (logic 0). The
IRQ
output pin will remain LOW until the SYSSTAT
register is read.
Bit 10
If Bit 10 is set to 1, then the reverse Park transforma-
tion will be formed in 3/3 mode. For Forward
transformations, this bit must be set to 1.
Table V. System Control (SYSCTRL) Registers
RESET
Default
Bit
Function
0
1
3
Auxiliary Channel Selection
Auxiliary Channel Selection
Enables U Channel Conversion
(1 = Enable) Two-/Three-Phase Mode
Enables AUX Channel Conversion
(0 = Disable, 1 = Enable)
Divide External Clock by 2
(0 = No, 1 = Yes)
Park Interrupt Enable
ADC Interrupt Enable
(0 = Disable, 1 = Enable)
IRQ
Pin Format (Edge or Level Based
Interrupt Requests) (0 = Edge)
Reverse Rotation (0 = 2/3, 1 = 3/3)
Forward Rotation (1 = Enable)
0
0
0
4
0
5
0
0
6
7
0
8
0
0
10
Table VI. SYSCTRL Auxiliary Channel Selection
Bit 0
Bit 1
Auxiliary Channels Converted
0
0
1
1
0
1
0
1
AUX0
AUX1
AUX2
AUX3
相关PDF资料 |
PDF描述 |
|---|---|
| ADMC201 | Motion Coprocessor(动作协处理器) |
| ADMC300 | High Performance DSP-Based Motor Controller |
| ADMC300-PB | High Performance DSP-Based Motor Controller |
| ADMC300BST | High Performance DSP-Based Motor Controller |
| ADMC300-ADVEVALKIT | Circular Connector; No. of Contacts:13; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADMC300 | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance DSP-Based Motor Controller |
| ADMC300-ADVEVALKIT | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance DSP-Based Motor Controller |
| ADMC300BST | 制造商:Analog Devices 功能描述:DSP Motor Controller 80-Pin TQFP 制造商:Analog Devices 功能描述:IC MOTOR CONTROLLER |
| ADMC300BSTZ | 制造商:Analog Devices 功能描述:DSP Motor Controller 80-Pin TQFP |
| ADMC300-PB | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance DSP-Based Motor Controller |
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