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参数资料
| 型号： | ADMC201AP |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Motion Coprocessor |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 3/15页 |
| 文件大小： | 146K |
| 代理商： | ADMC201AP |
ADMC201
REV. B
–3–
Table I. Timing Specifications (V
DD
= 5 V, 5%; T
A
= –4
0 C to +85 C)
Number
Symbol
Timing Requirements
Min
Max
Units
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
t
per
clk
t
pwh
clk
t
pwl
clk
t
su
csb_wrb
t
su
addr_wrb
t
su
data_wrb
t
hd
wrb_data
t
hd
wrb_addr
t
hd
wrb_csb
t
pwl
wrb
1
t
pwh
wrb
1
t
hd
wrb_clk_h
1
t
su
wrb_clk_h
1
t
su
wrb_clk_l
1
t
hd
clk_wrb_l
1
t
su
csb_rdb
t
su
addr_rdb
t
hd
rdb_addr
t
hd
rdb_csb
t
pwl
rdb
t
pwh
rdb
t
su
rdb_clk_h
t
hd
rdb_clk_h
t
pwl
resetb
CLK Period
CLK Pulsewidth, High
CLK Pulsewidth, Low
CS
Low before Falling Edge of
WR
ADDR Valid before Falling Edge of
WR
DATA Valid before Rising Edge of
WR
DATA Hold after Rising Edge of
WR
ADDR Hold after Rising Edge of
WR
CS
Hold after Rising Edge of
WR
WR
Pulsewidth, Low
WR
Pulsewidth, High
WR
Low after Rising Edge of CLK
WR
High before Rising Edge of CLK
WR
High before Falling Edge of CLK
WR
High after Falling Edge of CLK
CS
Low before Falling Edge of
RD
ADDR Valid before Falling Edge of
RD
ADDR Hold after Rising Edge of
RD
CS
Hold after Rising Edge of
RD
RD
Pulsewidth, Low
RD
Pulsewidth, High
RD
Low before Rising Edge of CLK
RD
Low after Rising Edge of CLK
RESET
Pulsewidth, Low
40
20
20
0
0
13
4.5
4.5
4.5
20
20
7
7
10
10
0
0
0
0
20
20
7.5
7.5
2
×
t
per
clk
160
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE
1
All WRITES to the ADMC201 must occur within 1 System Clock Cycle (0 wait states).
Number
Symbol
Switching Characteristics
Min
Max
Units
25
26
27
28
t
dly
rdb_data
t
hd
rdb_data
t
pwh
_pio
t
pwl
_pio
DATA Valid after Falling Edge of
RD
DATA Hold after Rising Edge of
RD
Digital I/O Pulsewidth, High
Digital I/O Pulsewidth, Low
23
ns
ns
ns
ns
0
2
×
t
per
clk
2
×
t
per
clk
1
2
3
CLK
Figure 1. Clock Input Timing
RESET
24
CLK
Figure 2. Reset Input Timing
11
4
5
6
7
10
12
15
13
9
8
14
CLK
CS
A0
–
A3
WR
DATA
NOTE:
ALL WRITES TO THE ADMC201 MUST OCCUR WITHIN
ONE SYSTEM CLOCK CYCLE (i.e., 0 WAIT STATES)
Figure 3. Write Cycle Timing Diagram
相关PDF资料 |
PDF描述 |
|---|---|
| ADMC201 | Motion Coprocessor(动作协处理器) |
| ADMC300 | High Performance DSP-Based Motor Controller |
| ADMC300-PB | High Performance DSP-Based Motor Controller |
| ADMC300BST | High Performance DSP-Based Motor Controller |
| ADMC300-ADVEVALKIT | Circular Connector; No. of Contacts:13; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADMC300 | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance DSP-Based Motor Controller |
| ADMC300-ADVEVALKIT | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance DSP-Based Motor Controller |
| ADMC300BST | 制造商:Analog Devices 功能描述:DSP Motor Controller 80-Pin TQFP 制造商:Analog Devices 功能描述:IC MOTOR CONTROLLER |
| ADMC300BSTZ | 制造商:Analog Devices 功能描述:DSP Motor Controller 80-Pin TQFP |
| ADMC300-PB | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance DSP-Based Motor Controller |
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