参数资料
| 型号： | ADN2814ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/28页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32LFCSP |
| 标准包装： | 1 |
| 类型： | 时钟和数据恢复（CDR），多路复用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 输入： | CML |
| 输出： | LVDS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 675MHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 托盘 |
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Data Sheet
ADN2814
Rev. C | Page 17 of 28
LOCK DETECTOR OPERATION
The lock detector on the ADN2814 has three modes of
operation: normal mode, REFCLK mode, and static LOL mode.
Normal Mode
In normal mode, the ADN2814 is a continuous rate CDR that
locks onto any data rate from 10 Mb/s to 675 Mb/s without the
use of a reference clock as an acquisition aid. In this mode, the
lock detector monitors the frequency difference between the
VCO and the input data frequency and deasserts the loss of lock
signal, which appears on Pin 16, LOL, when the VCO is within
250 ppm of the data frequency. This enables the D/PLL, which
pulls the VCO frequency in the remaining amount and acquires
phase lock. Once locked, if the input frequency error exceeds
1000 ppm (0.1%), the loss-of-lock signal is reasserted and
control returns to the frequency loop, which begins a new
frequency acquisition starting at the lowest point in the VCO
operating range, 10 MHz. The LOL pin remains asserted until
the VCO locks onto a valid input data stream to within
250 ppm frequency error. This hysteresis is shown in Figure 20.
LOL
0
–250
250
1000
fVCO ERROR
(ppm)
–1000
1
04949-020
Figure 20. Transfer Function of LOL
LOL Detector Operation Using a Reference Clock
In REFCLK mode, a reference clock is used as an acquisition aid
to lock the ADN2814 VCO. Lock-to-reference mode is enabled
by setting CTRLA[0] to 1. The user also needs to write to the
CTRLA[7:6] and CTRLA[5:2] bits to set the reference
frequency range and the divide ratio of the data rate with
respect to the reference frequency. For more details, see the
Reference Clock (Optional) section. In this mode, the lock
detector monitors the difference in frequency between the
divided down VCO and the divided down reference clock. The
loss-of-lock signal, which appears on Pin 16, LOL, is deasserted
when the VCO is within 250 ppm of the desired frequency. This
enables the D/PLL, which pulls the VCO frequency in the
remaining amount with respect to the input data and acquires
phase lock. Once locked, if the input frequency error exceeds
1000 ppm (0.1%), the loss-of-lock signal is reasserted and
control returns to the frequency loop, which reacquires with
respect to the reference clock. The LOL pin remains asserted
until the VCO frequency is within 250 ppm of the desired
frequency. This hysteresis is shown in Figure 20.
Static LOL Mode
The ADN2814 implements a static LOL feature, which indicates
if a loss-of-lock condition has ever occurred and remains
asserted, even if the ADN2814 regains lock, until the static LOL
bit is manually reset. The I2C register bit, MISC[4], is the static
LOL bit. If there is ever an occurrence of a loss-of-lock condition,
this bit is internally asserted to logic high. The MISC[4] bit
remains high even after the ADN2814 has reacquired lock to a
new data rate. This bit can be reset by writing a 1 followed by 0
to I2C Register Bit CTRLB[6]. Once reset, the MISC[4] bit
remains deasserted until another loss-of-lock condition occurs.
Writing a 1 to I2C Register Bit CTRLB[7] causes the LOL pin,
Pin 16, to become a static LOL indicator. In this mode, the LOL
pin mirrors the contents of the MISC[4] bit and has the
functionality described in the previous paragraph. The CTRLB[7]
bit defaults to 0. In this mode, the LOL pin operates in the
normal operating mode, that is, it is asserted only when the
ADN2814 is in acquisition mode and deasserts when the
ADN2814 has reacquired lock.
HARMONIC DETECTOR
The ADN2814 provides a harmonic detector, which detects
whether or not the input data has changed to a lower harmonic
of the data rate that the VCO is currently locked onto. For
example, if the input data instantaneously changes from OC-12,
622.08 Mb/s to an OC-3, 155.52 Mb/s bit stream, this could be
perceived as a valid OC-12 bit stream, because the OC-3 data
pattern is exactly 4× slower than the OC-12 pattern. Therefore,
if the change in data rate is instantaneous, a 101 pattern at OC-3
would be perceived by the ADN2814 as a 111100001111 pattern
at OC-12. If the change to a lower harmonic is instantaneous, a
typical CDR could remain locked at the higher data rate.
The ADN2814 implements a harmonic detector that automati-
cally identifies whether or not the input data has switched to a
lower harmonic of the data rate that the VCO is currently
locked onto. When a harmonic is identified, the LOL pin is
asserted and a new frequency acquisition is initiated. The
ADN2814 automatically locks onto the new data rate, and the
LOL pin is deasserted.
However, the harmonic detector does not detect higher
harmonics of the data rate. If the input data rate switches to a
higher harmonic of the data rate, then the VCO is currently
locked onto, the VCO loses lock, the LOL pin is asserted, and a
new frequency acquisition is initiated. The ADN2814
automatically locks onto the new data rate.
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