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| 型号： | ADN4668ARZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/12页 |
| 文件大小： | 0K |
| 描述： | IC RCVR LVDS DIFF 4CH 16SOIC |
| 标准包装： | 1,000 |
| 类型： | 线路接收器 |
| 驱动器/接收器数： | 0/4 |
| 规程： | LVDS |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
ADN4668
Rev. A | Page 11 of 12
THEORY OF OPERATION
The ADN4668 is a quad-channel line receiver for low voltage
differential signaling. It takes a differential input signal of
310 mV typical and converts it into a single-ended 3 V TTL/
CMOS logic signal.
A differential current input signal, received via a transmission
medium such as a twisted pair cable, develops a voltage across
a terminating resistor, RT. This resistor is chosen to match the
characteristic impedance of the medium, typically around 100 Ω.
The differential voltage is detected by the receiver and converted
back into a single-ended logic signal.
When the noninverting receiver input, RINx+, is positive with
respect to the inverting input, RINx (current flows through RT
from RINx+ to RINx), ROUTx is high. When the noninverting receiver
input, RIN+, is negative with respect to the inverting input, RINx
(current flows through RT from RINx to RINx+), ROUTx is low.
Using the ADN4667 as a driver, the received differential current
is between ±2.5 mA and ±4.5 mA (±3.1 mA typical), developing
between ±250 mV and ±450 mV across a 100 Ω termination
resistor. The received voltage is centered on the receiver offset
of 1.2 V. The noninverting receiver input is typically
(1.2 V + [310 mV/2]) = 1.355 V, and the inverting receiver input
is (1.2 V [310 mV/2]) = 1.045 V for Logic 1. For Logic 0, the
inverting and noninverting input voltages are reversed. Note
that because the differential voltage reverses polarity, the peak-to-
peak voltage swing across RT is twice the differential voltage.
Current-mode signaling offers considerable advantages over
voltage-mode signaling, such as the RS-422. The operating
current remains fairly constant with increased switching
frequency, whereas the operating current of voltage-mode
drivers increases exponentially in most cases. This increase is
caused by the overlap as internal gates switch between high and
low, causing currents to flow from VCC to ground. A current-
mode device reverses a constant current between its two outputs,
with no significant overlap currents.
This is similar to emitter-coupled logic (ECL) and positive emitter-
coupled logic (PECL), but without the high quiescent current of
ECL and PECL.
ENABLE INPUTS
The ADN4668 has active-high and active-low enable inputs that
put all the logic outputs into a high impedance state when disabled,
reducing device current consumption from 9 mA typical to 1 mA
typical. See Table 5 for a truth table of the enable inputs.
Table 5. Enable Inputs Truth Table
EN
RINx+
RINx
ROUTx
High
Low or Open
1.045 V
1.355 V
0
High
Low or Open
1.355 V
1.045 V
1
Any other combination
of EN and EN
X
High-Z
APPLICATIONS INFORMATION
Figure 22 shows a typical application for point-to-point data
transmission using the ADN4667 as the driver and the ADN4668
as the receiver.
07
23
7-
02
3
DIN
DOUT
RT
100
EN
1/4 ADN4668
1/4 ADN4667
RINx+
RINx–
DOUTy+
DOUTy–
GND
EN
GND
Figure 22. Typical Application Circuit
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