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| 型号： | ADP1111ANZ-12 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 12/15页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK BST INV 12V .2A 8DIP |
| 标准包装： | 50 |
| 类型： | 降压（降压），升压（升压），反相 |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 12V |
| 输入电压： | 2 V ~ 30 V |
| 频率 - 开关： | 72kHz |
| 电流 - 输出： | 200mA |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 包装： | 管件 |
| 供应商设备封装： | 8-PDIP |
ADP1111
This occurs in the step-up mode when the following condition is
met:
V IN
V IN
R LIM
(EXTERNAL)
I LIM
V OUT + V DIODE
V IN ? V SW
<
1
1 ? DC
Q3
R1
80 Ω
(INTERNAL)
where DC is the ADP1111’s duty cycle. When this relationship
exists, the inductor current does not go all the way to zero
during the time that the switch is OFF. When the switch turns
ADP1111
72kHz
OSC
DRIVER
I Q1
200
Q2
SW1
Q1
POWER
SWITCH
on for the next cycle, the inductor current begins to ramp up
from the residual level. If the switch ON time remains constant,
the inductor current will increase to a high level (see Figure 24).
This increases output ripple and can require a larger inductor
and capacitor. By controlling switch current with the I LIM
resistor, output ripple current can be maintained at the design
values. Figure 25 illustrates the action of the I LIM circuit.
200mA/div
Figure 24.
SW2
Figure 26. ADP1111 Current Limit Operation
The delay through the current limiting circuit is approximately
1 μ s. If the switch ON time is reduced to less than 3 μ s, accuracy
of the current trip-point is reduced. Attempting to program a
switch ON time of 1 μ s or less will produce spurious responses
in the switch ON time; however, the ADP1111 will still provide
a properly regulated output voltage.
PROGRAMMING THE GAIN BLOCK
The gain block of the ADP1111 can be used as a low-battery
detector, error amplifier or linear post regulator. The gain block
consists of an op amp with PNP inputs and an open-collector
NPN output. The inverting input is internally connected to the
ADP1111’s 1.25 V reference, while the noninverting input is
available at the SET pin. The NPN output transistor will sink
about 300 μ A.
Figure 27a shows the gain block configured as a low-battery
monitor. Resistors R1 and R2 should be set to high values to
reduce quiescent current, but not so high that bias current in
the SET input causes large errors. A value of 33 k Ω for R2 is a
good compromise. The value for R1 is then calculated from the
formula:
R 1 =
V LOBATT ? 1.25 V
1.25 V
R 2
where V LOBATT is the desired low battery trip point. Since the
200mA/div
gain block output is an open-collector NPN, a pull-up resistor
should be connected to the positive logic power supply.
5V
Figure 25.
V IN
R L
47k
The internal structure of the I LIM circuit is shown in Figure 26.
Q1 is the ADP1111’s internal power switch that is paralleled by
sense transistor Q2. The relative sizes of Q1 and Q2 are scaled
V BAT
R1
1.25V
REF
SET
ADP1111
AO
TO
PROCESSOR
V LB –1.25V
35.1 μ A
so that I Q2 is 0.5% of I Q1 . Current flows to Q2 through an
internal 80 Ω resistor and through the R LIM resistor. These two
resistors parallel the base-emitter junction of the oscillator-
disable transistor, Q3. When the voltage across R1 and R LIM
33k
R2
GND
R1= –––––––––
V LB = BATTERY TRIP POINT
exceeds 0.6 V, Q3 turns on and terminates the output pulse. If
REV. A
only the 80 Ω internal resistor is used (i.e. the I LIM pin is
connected directly to V IN ), the maximum switch current will be
1.5 A. Figure 6 gives R LIM values for lower current-limit values.
–12 –
Figure 27a. Setting the Low Battery Detector Trip Point
REV. 0
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