参数资料
型号: ADP1752ACPZ-1.8-R7
厂商: Analog Devices Inc
文件页数: 14/20页
文件大小: 0K
描述: IC REG LDO 1.8V .8A 16LFCSP
标准包装: 1
稳压器拓扑结构: 正,固定式
输出电压: 1.8V
输入电压: 最高 3.6V
电压 - 压降(标准): 0.07V @ 800mA
稳压器数量: 1
电流 - 输出: 800mA(最小值)
电流 - 限制(最小): 1A
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-VQFN 裸露焊盘,CSP
供应商设备封装: 16-LFCSP-VQ EP(4x4)
包装: 标准包装
其它名称: ADP1752ACPZ-1.8-R7DKR

ADP1752/ADP1753
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP1752 / ADP1753 are designed for operation with small,
space-saving ceramic capacitors, but they can function with most
commonly used capacitors as long as care is taken with the
effective series resistance (ESR) value. The ESR of the output
capacitor affects the stability of the LDO control loop. A mini-
mum of 3.3 μF capacitance with an ESR of 500 mΩ or less is
recommended to ensure the stability of the ADP1752 / ADP1753 .
Transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP1752 / ADP1753 to
large changes in load current. Figure 33 and Figure 34 show the
transient responses for output capacitance values of 4.7 μF and
22 μF, respectively.
Data Sheet
Input Bypass Capacitor
Connecting a 4.7 μF capacitor from the VIN pin to GND reduces
the circuit sensitivity to printed circuit board (PCB) layout,
especially when long input traces or high source impedance
are encountered. If output capacitance greater than 4.7 μF is
required, it is recommended that the input capacitor be increased
to match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitors can be used with the
ADP1752 / ADP1753 , as long as they meet the minimum
capacitance and maximum ESR requirements. Ceramic
capacitors are manufactured with a variety of dielectrics,
each with different behavior over temperature and applied
voltage. Capacitors must have a dielectric adequate to ensure
the minimum capacitance over the necessary temperature
T
I LOAD
range and dc bias conditions. X5R or X7R dielectrics with a
voltage rating of 6.3 V or 10 V are recommended. Y5V and
Z5U dielectrics are not recommended, due to their poor tempera-
1
1mA TO 800mA LOAD STEP, 2V/μs, 500mA/DIV
ture and dc bias characteristics.
Figure 35 shows the capacitance vs. voltage bias characteristics
of an 0805 case, 4.7 μF, 10 V, X5R capacitor. The voltage stability
2
V OUT
50mV/DIV
V IN = 3.6V, V OUT = 1.5V
C IN = C OUT = 4.7μF
of a capacitor is strongly influenced by the capacitor size and
voltage rating. In general, a capacitor in a larger package or with
a higher voltage rating exhibits better stability. The temperature
variation of the X5R dielectric is about ±15% over the ?40°C to
+85°C temperature range and is not a function of package size
or voltage rating.
W M1μs
CH1 500mA ? BW CH2 50mV
B
T 11.6%
A CH1
380mA
5
MURATA P/N GRM219R61A475KE34
Figure 33. Output Transient Response, C OUT = 4.7 μF
4
T
I LOAD
3
1mA TO 800mA LOAD STEP, 2V/μs, 500mA/DIV
2
1
1
2
V OUT
0
0
2
4
6
8
10
20mV/DIV
VOLTAGE BIAS (V)
W M1μs
A CH1
530mA
CH1 500mA ? BW CH2 20mV
B
V IN = 3.6V, V OUT = 1.5V
C IN = C OUT = 22μF
T 12.2%
Figure 35. Capacitance vs. Voltage Bias Characteristics
Equation 3 can be used to determine the worst-case capacitance
accounting for capacitor variation over temperature, component
Figure 34. Output Transient Response, C OUT = 22 μF
tolerance, and voltage.
C EFF = C OUT × (1 ? TEMPCO ) × (1 ? TOL )
where:
C EFF is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
Rev. F | Page 14 of 20
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