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参数资料
| 型号： | ADP1755-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/20页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL 1.2V SET ADP1755 |
| 标准包装： | 1 |
| 每 IC 通道数： | 1 - 单 |
| 输出电压： | 0.75 ~ 3V |
| 电流 - 输出： | 1.2A |
| 输入电压： | 1.6 ~ 3.6V |
| 稳压器类型： | 正，可调式 |
| 工作温度： | -40°C ~ 125°C |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP1755 |
Data Sheet
ADP1754/ADP1755
1
V IN
1V/DIV
T
V OUT
500mV/DIV
PG
1V/DIV
REVERSE CURRENT PROTECTION FEATURE
The ADP1754/ADP1755 have additional circuitry to protect
against reverse current flow from VOUT to VIN. For a typical
LDO with a PMOS pass device, there is an intrinsic body diode
between VIN and VOUT. When V IN is greater than V OUT , this
diode is reverse-biased. If V OUT is greater than V IN , the intrinsic
diode becomes forward-biased and conducts current from VOUT
to VIN, potentially causing destructive power dissipation. The
reverse current protection circuitry detects when V OUT is greater
2
CH1 1.0V BW
CH3 1.0V BW
V OUT = 1.5V
C IN = C OUT = 4.7μF
CH2 500mV BW M40.0μs A CH3 900mV
T 50.40%
than V IN and reverses the direction of the intrinsic diode connec-
tion, reverse-biasing the diode. The gate of the PMOS pass
device is also connected to VOUT, keeping the device off.
Figure 30. Typical PG Behavior vs. V OUT , V IN Rising (V OUT = 1.5 V)
T
V IN
1V/DIV
differential.
4000
3500
3000
2500
1
V OUT
2000
500mV/DIV
1500
1000
PG
500
2
V OUT = 1.5V
1V/DIV
0
C IN = C OUT = 4.7μF
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
3.6
CH1 1.0V BW
CH3 1.0V BW
CH2 500mV BW M40.0μs
T 50.40%
A CH3
900mV
V OUT – V IN (V)
Figure 32. Reverse Current vs. V OUT ? V IN
Figure 31. Typical PG Behavior vs. V OUT , V IN Falling (V OUT = 1.5 V)
Rev. F | Page 13 of 20
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