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参数资料
| 型号： | ADP1755-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/20页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL 1.2V SET ADP1755 |
| 标准包装： | 1 |
| 每 IC 通道数： | 1 - 单 |
| 输出电压： | 0.75 ~ 3V |
| 电流 - 输出： | 1.2A |
| 输入电压： | 1.6 ~ 3.6V |
| 稳压器类型： | 正，可调式 |
| 工作温度： | -40°C ~ 125°C |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP1755 |
ADP1754/ADP1755
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP1754/ADP1755 are designed for operation with small,
space-saving ceramic capacitors, but they can function with most
commonly used capacitors as long as care is taken with the
effective series resistance (ESR) value. The ESR of the output
capacitor affects the stability of the LDO control loop. A mini-
mum of 3.3 μF capacitance with an ESR of 500 m? or less is
recommended to ensure the stability of the ADP1754/ADP1755.
Transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP1754/ADP1755 to
large changes in load current. Figure 33 and Figure 34 show the
transient responses for output capacitance values of 4.7 μF and
22 μF, respectively.
Data Sheet
Input Bypass Capacitor
Connecting a 4.7 μF capacitor from the VIN pin to GND
reduces the circuit sensitivity to printed circuit board (PCB)
layout, especially when long input traces or high source
impedance are encountered. If output capacitance greater than
4.7 μF is required, it is recommended that the input capacitor be
increased to match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitors can be used with the
ADP1754, as long as they meet the minimum capacitance and
maximum ESR requirements. Ceramic capacitors are manufac-
tured with a variety of dielectrics, each with different behavior
over temperature and applied voltage. Capacitors must have a
dielectric adequate to ensure the minimum capacitance over the
necessary temperature range and dc bias conditions. X5R or
T
I LOAD
X7R dielectrics with a voltage rating of 6.3 V or 10 V are recom-
mended. Y5V and Z5U dielectrics are not recommended, due
to their poor temperature and dc bias characteristics.
1
1mA TO 1.2A LOAD STEP, 2.5A/μs, 500mA/DIV
of an 0805 case, 4.7 μF, 10 V, X5R capacitor. The voltage stability
of a capacitor is strongly influenced by the capacitor size and
2
V OUT
50mV/DIV
V IN = 3.6V, V OUT = 1.5V
C IN = C OUT = 4.7μF
voltage rating. In general, a capacitor in a larger package or with
a higher voltage rating exhibits better stability. The temperature
variation of the X5R dielectric is about ±15% over the ?40°C to
+85°C temperature range and is not a function of package size
or voltage rating.
5
CH1 500mA BW CH2 50mV
B
W M1μs
A CH1
380mA
MURATA P/N GRM219R61A475KE34
T 11.2%
Figure 33. Output Transient Response, C OUT = 4.7 μF
T
I LOAD
1mA TO 1.2A LOAD STEP, 2.5A/μs, 500mA/DIV
4
3
2
1
1
2
V OUT
20mV/DIV
0
0
2
4
6
8
10
VOLTAGE BIAS (V)
V IN = 3.6V, V OUT = 1.5V
C IN = C OUT = 22μF
Figure 35. Capacitance vs. Voltage Bias Characteristics
CH1 500mA BW CH2 20mV
B
W M1μs
T 11.0%
A CH1
340mA
Equation 3 can be used to determine the worst-case capacitance,
accounting for capacitor variation over temperature, component
Figure 34. Output Transient Response, C OUT = 22 μF
tolerance, and voltage.
C EFF = C OUT × (1 ? TEMPCO ) × (1 ? TOL )
where:
C EFF is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
Rev. F | Page 14 of 20
(3)
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