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| 型号： | ADP1755-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/20页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL 1.2V SET ADP1755 |
| 标准包装： | 1 |
| 每 IC 通道数： | 1 - 单 |
| 输出电压： | 0.75 ~ 3V |
| 电流 - 输出： | 1.2A |
| 输入电压： | 1.6 ~ 3.6V |
| 稳压器类型： | 正，可调式 |
| 工作温度： | -40°C ~ 125°C |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP1755 |
ADP1754/ADP1755
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
PIN 1
Data Sheet
VIN 1
VIN 2
VIN 3
EN 4
INDICATOR
ADP1754
TOP VIEW
(Not to Scale)
12 VOUT
11 VOUT
10 VOUT
9 SENSE
VIN 1
VIN 2
VIN 3
EN 4
INDICATOR
ADP1755
TOP VIEW
(Not to Scale)
12 VOUT
11 VOUT
10 VOUT
9 ADJ
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE CONNECTED TO THE GROUND PLANE ON THE BOARD.
Figure 3. ADP1754 Pin Configuration
Table 5. Pin Function Descriptions
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE CONNECTED TO THE GROUND PLANE ON THE BOARD.
Figure 4. ADP1755 Pin Configuration
ADP1754
ADP1755
Pin No.
1, 2, 3, 15,
16
4
Pin No.
1, 2, 3, 15,
16
4
Mnemonic
VIN
EN
Description
Regulator Input Supply. Bypass VIN to GND with a 4.7 μF or greater capacitor. Note that all five
VIN pins must be connected to the source.
Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For
automatic startup, connect EN to VIN.
5
5
PG
Power Good. This open-drain output requires an external pull-up resistor to VIN. If the part is in
shutdown mode, current-limit mode, thermal shutdown, or if it falls below 90% of the nominal
output voltage, PG immediately transitions low.
6
7
8
9
6
7
8
N/A
GND
SS
NC
SENSE
Ground.
Soft Start. A capacitor connected to this pin determines the soft start time.
Not Connected. No internal connection.
Sense. This pin measures the actual output voltage at the load and feeds it to the error
amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop
between the regulator output and the load.
N/A
10, 11, 12,
13, 14
17 (EPAD)
9
10, 11, 12,
13, 14
17 (EPAD)
ADJ
VOUT
Exposed
paddle
(EPAD)
Adjust. A resistor divider from VOUT to ADJ sets the output voltage.
Regulated Output Voltage. Bypass VOUT to GND with a 4.7 μF or greater capacitor. Note that all
five VOUT pins must be connected to the load.
The exposed pad on the bottom of the LFCSP package enhances thermal performance and is
electrically connected to GND inside the package. It is recommended that the exposed pad be
connected to the ground plane on the board.
Rev. F | Page 6 of 20
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