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| 型号： | ADP1823-EVAL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADP1823 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 1.2V |
| 电流 - 输出： | 15A |
| 输入电压： | 5.5 ~ 20 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP1823 |
| 产品目录页面： | 791 (CN2011-ZH PDF) |
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ADP1823
COMPENSATING THE VOLTAGE MODE BUCK
LC FILTER BODE PLOT
REGULATOR
Assuming the LC filter design is complete, the feedback control
system can then be compensated. Good compensation is critical
to proper operation of the regulator. Calculate the quantities in
GAIN
0dB
f LC
–40dB/dec
f ESR
f CO
f SW
FREQUENCY
Equation 19 through Equation 47 to derive the compensation
values. The goal is to guarantee that the voltage gain of the buck
converter crosses unity at a slope that provides adequate phase
margin for stable operation. Additionally, at frequencies above
the crossover frequency, f CO , guaranteeing sufficient gain margin
and attenuation of switching noise are important secondary
goals. For initial practical designs, a good choice for the
crossover frequency is one tenth of the switching frequency.
First calculate
PHASE
0°
–20dB/dec
A FILTER
f CO =
f SW
10
(19)
This gives sufficient frequency range to design a compensation
that attenuates switching artifacts, while also giving sufficient
control loop bandwidth to provide good transient response.
The output LC filter is a resonant network that inflicts two poles
upon the response at a frequency f LC , so next calculate
–90°
–180°
Φ FILTER
f LC =
1
2 π LC
(20)
Figure 26. LC Filter Bode Plot
To compensate the control loop, the gain of the system must be
Generally, the LC corner frequency is about two orders of
magnitude below the switching frequency, and, therefore, about
brought back up so that it is 0 dB at the desired crossover
frequency. Some gain is provided by the PWM modulation itself.
A MOD = 20 log ?
?
?
one order of magnitude below crossover. To achieve sufficient
phase margin at crossover to guarantee stability, the design
must compensate for the two poles at the LC corner frequency
? V IN
?
? V RAMP
?
?
(23)
with two zeros to boost the system phase prior to crossover. The
For systems using the internal oscillator, this becomes
A MOD = 20 log ?
? 1 . 3 V
?
?
two zeros require an additional pole or two above the crossover
frequency to guarantee adequate gain margin and attenuation of
switching noise at high frequencies.
? V IN
?
?
?
(24)
Depending on component selection, one zero may already be
generated by the equivalent series resistance (ESR) of the output
capacitor. Calculate this zero corner frequency, f ESR , as
Note that if the converter is being synchronized, the ramp
voltage, V RAMP , is lower than 1.3 V by the percentage of
frequency increase over the nominal setting of the FREQ pin.
f ESR =
V RAMP = 1 . 3 V ?
?
?
1
2 π R ESR C OUT
(21)
? 2 f FREQ
?
? f SYNC
?
?
(25)
The gain of the LC filter at crossover can be linearly
approximated from Figure 26 as
A FILTER = A LC + A ESR
The factor of 2 in the numerator takes into account that the
SYNC frequency is divided by 2 to generate the switching
frequency. For example, if the FREQ pin is set high for the
600 kHz range and a 2 MHz SYNC signal is applied, the ramp
A FILTER = ? 40 dB × log ? ESR
? ? 20 dB × log ? f CO
? f
?
? ESR
?
?
? f
?
? f LC
? ?
?
?
?
(22)
voltage is 0.78 V. The gain of the modulator is increased by
4.4 dB in this example.
If f ESR ≈ f CO , add another 3 dB to account for the local difference
between the exact solution and the linear approximation.
Rev. D | Page 19 of 32
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