参数资料
型号: ADP1823-EVAL
厂商: Analog Devices Inc
文件页数: 20/32页
文件大小: 0K
描述: BOARD EVAL FOR ADP1823
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 1.2V
电流 - 输出: 15A
输入电压: 5.5 ~ 20 V
稳压器拓扑结构: 降压
频率 - 开关: 300kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ADP1823
产品目录页面: 791 (CN2011-ZH PDF)
ADP1823
The rest of the system gain is needed to reach 0 dB at crossover.
The total gain of the system, therefore, is given by
GAIN
LC FILTER BODE PLOT
PHASE CONTRIBUTION AT CROSSOVER
OF VARIOUS ESR ZERO CORNERS
A T = A MOD + A FILTER + A COMP
where:
(26)
0dB
f LC f ESR1 f ESR2 f ESR3 f CO
–40dB/dec
f SW
FREQUENCY
A MOD is the gain of the PWM modulator.
A FILTER is the gain of the LC filter including the effects of
the ESR zero.
A COMP is the gain of the compensated error amplifier.
Additionally, the phase of the system must be brought back up
to guarantee stability. Note from the Bode plot of the filter that
the LC contributes ?180° of phase shift. Additionally, because
the error amplifier is an integrator at low frequency, it contributes
an initial ?90°. Therefore, before adding compensation or
accounting for the ESR zero, the system is already down ?270°.
To avoid loop inversion at crossover, or ?180° phase shift, a
good initial practical design is to require a phase margin of 60°,
PHASE
–20dB/dec
which is therefore an overall phase loss of ?120° from the initial
low frequency dc phase. The goal of the compensation is to
boost the phase back up from ?270° to ?120° at crossover.
Two common compensation schemes are used, which are
sometimes referred to as Type II or Type III compensation,
depending on whether the compensation design includes two
–90°
–180°
Φ 1
Φ 2
Φ 3
or three poles. (Dominant pole compensation, or single pole
compensation, is referred to as Type I compensation, but
unfortunately, it is not very useful for dealing successfully with
switching regulators.)
Figure 27. LC Filter Bode Plot
The following equations were used for the calculation of the
compensation components as shown in Figure 28 and Figure 29:
If the zero produced by the ESR of the output capacitor provides
sufficient phase boost at crossover, Type II compensation is
adequate. If the phase boost produced by the ESR of the output
capacitor is not sufficient, another zero is added to the compensa-
tion network, and thus Type III is used.
f Z 1 =
f Z 2 =
1
2 π R Z C I
1
2 π C FF ( R TOP + R FF )
(27)
(28)
In Figure 27, the location of the ESR zero corner frequency
gives significantly different net phase at the crossover frequency.
Use the following guidelines for selecting between Type II and
f P 1 =
2 π R Z
1
C I C HF
C I + C HF
(29)
Type III compensators:
If f ESRZ ≤ f CO /2, use Type II compensation.
f P 2 =
1
2 π R FF C FF
(30)
If f ESRZ > f CO /2, use Type III compensation.
where:
f Z1 is the zero produced in the Type II compensation.
f Z2 is the zero produced in the Type III compensation.
f P1 is the pole produced in the Type II compensation.
f P2 in the pole produced in the Type III compensation.
Rev. D | Page 20 of 32
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