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| 型号： | ADP1823-EVAL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADP1823 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 1.2V |
| 电流 - 输出： | 15A |
| 输入电压： | 5.5 ~ 20 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ADP1823 |
| 产品目录页面： | 791 (CN2011-ZH PDF) |
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ADP1823
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
FB1
SYNC
FREQ
GND
UV2
FB2
COMP2
TRK2
1
2
3
4
5
6
7
8
PIN 1
INDICATOR
ADP1823
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
POK1
BST1
DH1
SW1
CSL1
PGND1
DL1
PV
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Mnemonic
FB1
SYNC
FREQ
GND
UV2
FB2
COMP2
TRK2
SS2
POK2
BST2
DH2
SW2
CSL2
PGND2
DL2
PV
DL1
PGND1
CSL1
SW1
DH1
BST1
Description
Feedback Voltage Input for Channel 1. Connect a resistor divider from the buck regulator output to GND and
tie the tap to FB1 to set the output voltage.
Frequency Synchronization Input. Accepts external signal between 600 kHz and 1.2 MHz or between 1.2 MHz
and 2 MHz depending on whether FREQ is low or high, respectively. Connect SYNC to ground if not used.
Frequency Select Input. Low for 300 kHz or high for 600 kHz.
Ground. Connect to a ground plane directly beneath the ADP1823. Tie the bottom of the feedback dividers to
this GND.
Input to the POK2 Undervoltage and Overvoltage Comparators. For the default thresholds, connect UV2
directly to FB2. For some tracking applications, connect UV2 to an extra tap on the FB2 voltage divider string.
Feedback Voltage Input for Channel 2. Connect a resistor divider from the buck regulator output to GND and
tie the tap to FB2 to set the output voltage.
Error Amplifier Output for Channel 2. Connect an RC network from COMP2 to FB2 to compensate Channel 2.
Tracking Input for Channel 2. To track a master voltage, drive TRK2 from a voltage divider to the master
voltage. If the tracking function is not used, connect TRK2 to VREG.
Soft Start Control Input. Connect a capacitor from SS2 to GND to set the soft start period.
Open-Drain Power OK Output for Channel 2. Sinks current when UV2 is out of regulation. Connect a pull-up
resistor from POK2 to VREG.
Boost Capacitor Input for Channel 2. Powers the high-side gate driver, DH2. Connect a 0.22 μF to 0.47 μF
ceramic capacitor from BST2 to SW2 and a Schottky diode from PV to BST2.
High-Side (Switch) Gate Driver Output for Channel 2.
Switch Node Connection for Channel 2.
Current Sense Comparator Inverting Input for Channel 2. Connect a resistor between CSL2 and SW2 to set
the current-limit offset.
Ground for Channel 2 Gate Driver. Connect to a ground plane directly beneath the ADP1823.
Low-Side (Synchronous Rectifier) Gate Driver Output for Channel 2.
Positive Input Voltage for Gate Driver DL1 and Gate Driver DL2. Connect PV to VREG and bypass to ground
with a 1 μF capacitor.
Low-Side (Synchronous Rectifier) Gate Driver Output for Channel 1.
Ground for Channel 1 Gate Driver. Connect to a ground plane directly beneath the ADP1823.
Current Sense Comparator Inverting Input for Channel 1. Connect a resistor between CSL1 and SW1 to set
the current-limit offset.
Switch Node Connection for Channel 1.
High-Side (Switch) Gate Driver Output for Channel 1.
Boost Capacitor Input for Channel 1. Powers the high-side gate driver, DH1. Connect a 0.22 μF to 0.47 μF
ceramic capacitor from BST1 to SW1 and a Schottky diode from PV to BST1.
Rev. D | Page 7 of 32
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